ECOG1X5A5L CYAN, ECOG1X5A5L Datasheet - Page 24

• Manufacturer Part Number: ECOG1X5A5L
• Description: MCU, 16BIT, 512K FLASH, USB, 68QFN
• Manufacturer: CYAN

Specifications of ECOG1X5A5L

• Core Size: 16bit
• No. Of I/o's: 32
• Program Memory Size: 512KB
• Ram Memory Size: 24KB
• Cpu Speed: 70MHz
• Oscillator Type: External, Internal
• No. Of Timers: 5
• No. Of Pwm Channels: 2
• Rohs Compliant: Yes
• Controller Family/series: ECOG1X

Version 1.17
Peripherals
System Support Module
24
This section gives a brief description of the eCOG1X device peripherals. For a complete description,
see the eCOG1X User Manual.
The System Support Module (SSM) controls all internal clocks and reset signals for the
eCOG1X CPU and peripherals.
The SSM has four principal functional blocks.
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Clock sources
Five clock sources are used to provide all eCOG1X internal system clocks. Two crystal oscillators
provide accurate reference clocks, which can be driven into two PLL multipliers providing a further two
reference clocks. A relaxation oscillator provides a fifth clock source that requires no external
components and provides very short startup times. The programmable PLL multipliers allow a wide
range of clock frequencies to be generated.
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CPU/Memory Clock Selector
The CPU/memory clock selector contains logic for detecting valid running clocks and selecting the
master clock from the available clock signals. It also provides a prescaler and divider to control the
frequencies of the clocks to both the CPU and the memory subsystem.
Divider Chains
Five 16-bit divider chains, each clocked from one of the principal system clock sources, provide the
source clock signals for all the internal peripheral modules. The divider chains provide a range of clock
frequencies to the peripherals, to be selected according to the speed of the peripheral or any low
power requirements of the application. The output frequency division factors range from ÷2 to ÷2
Peripheral Clock Selectors
Each of the 16 outputs from the five divider chains are fed into the peripheral clock selector block,
giving a total of 80 possible clock frequencies for each peripheral from the five clock sources. For each
peripheral module, one output from one of the five divider chains is selected to provide its clock signal.
Most peripherals also have a 4-bit prescaler providing a further frequency division of ÷1 to ÷16.
Summary
The source clock and peripheral clock selections provide an extremely flexible system for controlling
independently the frequencies of the clock signals to each peripheral. This has significant benefits in
managing the power consumption of the device. High frequency clocks can be provided selectively to
the high speed peripherals that need them, while low speed peripherals can use low frequency clocks,
reducing unnecessary power consumption. Unused peripherals can have their clock stopped
altogether, reducing their supply current to a minimum.
The following diagram shows the complete eCOG1X SSM clocking scheme.
Clock oscillators and PLL multipliers
CPU/memory clock selector.
Divider chains.
Peripheral clock selectors.
Low reference oscillator.
A low power 32kHz oscillator using an external quartz watch crystal.
Low PLL.
Phase locked loop with a programmable multiplication factor from x2 to x305. The low reference
oscillator provides the clock input to the low PLL.
Relaxation oscillator.
A simple RC oscillator that requires no external components for low cost systems. On the
208BGA packaged devices, an external resistor can be used to adjust the oscillator frequency, in
the range 1-11MHz.
High reference oscillator.
A high performance oscillator using an external 5-10MHz quartz crystal (8MHz nominal).
High PLL.
Phase locked loop with a programmable multiplication factor from x2 to x50. The high PLL can be
driven from the high reference oscillator, the relaxation oscillator, or the output of the low PLL.
eCOG and CyanIDE are registered trademarks of Cyan Holdings plc
eCOG1X Microcontroller Product Family
www.cyantechnology.com
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11 February 2010
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