ECOG1X5A5L CYAN, ECOG1X5A5L Datasheet - Page 7

• Manufacturer Part Number: ECOG1X5A5L
• Description: MCU, 16BIT, 512K FLASH, USB, 68QFN
• Manufacturer: CYAN

Specifications of ECOG1X5A5L

• Core Size: 16bit
• No. Of I/o's: 32
• Program Memory Size: 512KB
• Ram Memory Size: 24KB
• Cpu Speed: 70MHz
• Oscillator Type: External, Internal
• No. Of Timers: 5
• No. Of Pwm Channels: 2
• Rohs Compliant: Yes
• Controller Family/series: ECOG1X

eCOG1X8A5
1
2
11 February 2010
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
The 68QFN package has a large central body contact which forms the GND pad. This is listed as pin 69.
Pins labelled NC may be connected internally and must be left open-circuit.
Pin Diagram
68 pin QFN - A package (top view).
Pin List
Description
EMAC_TXD0 / PortA_0
EMAC_TXD1 / PortA_1
EMAC_TXD2 / PortA_2
EMAC_TXD3 / PortA_3
VDD
EMAC_RXD0 / PortA_4
EMAC_RXD1 / PortA_5
EMAC_RXD2 / PortA_6
EMAC_RXD3 / PortA_7
IVDD
EMAC_CLKT / PortB_0
EMAC_CLKR / PortB_1
EMAC_RXER / PortB_2
EMAC_RXDV / PortB_3
EMAC_COL / PortB_4
VDD
VPP
EMAC_RXER / PortB_2
EMAC_RXD0 / PortA_4
EMAC_RXD1 / PortA_5
EMAC_RXD2 / PortA_6
EMAC_RXD3 / PortA_7
EMAC_CLKR / PortB_1
EMAC_RXDV / PortB_3
EMAC_TXD0 / PortA_0
EMAC_TXD1 / PortA_1
EMAC_TXD2 / PortA_2
EMAC_TXD3 / PortA_3
EMAC_CLKT / PortB_0
EMAC_COL / PortB_4
IVDD
VDD
VDD
VPP
eCOG and CyanIDE are registered trademarks of Cyan Holdings plc
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
Pin
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
eCOG1X Microcontroller Product Family
eCOG1X8A5
69
Description
EMAC_CRS / PortB_5
EMAC_TXEN / PortB_6
EMAC_TXER / PortB_7
eICE_CLOCK / JTCLK
eICE_LOADB / JTMS
eICE_MOSI / JTDI
eICE_MISO / JTDO
IVDD
PortC_0
PortC_1
PortC_2
PortC_3
VDD
PortT_0
PortT_1
PortT_2
PortT_3
Table 6: eCOG1X8A5 pin list
GND
www.cyantechnology.com
Pin
35
36
37
38
40
41
42
43
44
45
46
47
48
49
51
39
50
PortE_0
PortE_1
PortE_2
PortD_3
Description
VDD
PortE_3
PortE_4
PortE_5
PortE_6
PortE_7
IVDD
nTest
PortD_0
PortD_1
PortD_2
VDD
nReset
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
nReset
VDD
PortD_3
PortD_2
PortD_1
PortD_0
nTest
IVDD
PortE_7
PortE_6
PortE_5
PortE_4
PortE_3
PortE_2
PortE_1
PortE_0
VDD
Pin
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
Description
VDD
PortN_0
PortN_1
PortN_2
PortN_3
PortN_4
PortN_5
PortN_6
PortN_7
NC
AVDD
FIL
AVDD
Low_XTAL_In
Low_XTAL_Out
High_XTAL_In
High_XTAL_Out
GND
1
Version 1.17
7