ECOG1X5A5L CYAN, ECOG1X5A5L Datasheet - Page 68

• Manufacturer Part Number: ECOG1X5A5L
• Description: MCU, 16BIT, 512K FLASH, USB, 68QFN
• Manufacturer: CYAN

Specifications of ECOG1X5A5L

• Core Size: 16bit
• No. Of I/o's: 32
• Program Memory Size: 512KB
• Ram Memory Size: 24KB
• Cpu Speed: 70MHz
• Oscillator Type: External, Internal
• No. Of Timers: 5
• No. Of Pwm Channels: 2
• Rohs Compliant: Yes
• Controller Family/series: ECOG1X

Version 1.17
68
Symbol
Symbol
EHI_D0..D16/D32
EHI_D0..D16/D32
T
T
t
t
t
t
t
t
N
t
t
N
N
t
DH
CLK
R1
R2
R3
DV
DS
A1
A2
BIT
DI
DMA mode - eCOG1X as slave
Serial Peripheral Interface (SPI)
The tables below for the SPI function use the following symbols for time periods defined by bit fields in
the DUSART registers.
S
H
L
EHI_REQ
EHI_REQ
EHI_ACK
EHI_ACK
Parameter
Delay time EHI_REQ output active to EHI_ACK input active
Delay time EHI_ACK input active to EHI_REQ output inactive
Delay time EHI_ACK input inactive to EHI_REQ output active
Minimum EHI_ACK input active width
Minimum EHI_ACK input inactive width
Delay time EHI_ACK input active to data output valid
Delay time EHI_ACK input inactive to data output invalid
Setup time data input valid to EHI_ACK input inactive
Hold time EHI_ACK input inactive to data input invalid
Description
DUSART peripheral input clock period
DUSART sample period (0..255)
DUSART serial clock active period (0..255)
DUSART serial clock inactive period (0..255)
Serial data bit time (master mode)
eCOG and CyanIDE are registered trademarks of Cyan Holdings plc
t
t
R1
R1
Figure 19: EHI DMA slave write cycle timing diagram
Figure 18: EHI DMA slave read cycle timing diagram
Table 35: AC characteristics - EHI DMA slave mode
t
DV
t
t
R2
R2
eCOG1X Microcontroller Product Family
t
t
A1
A1
t
DS
data(n)
data(n)
Table 36: DUSART clock symbols
www.cyantechnology.com
t
t
DH
DI
t
t
R3
R3
t
t
A2
A2
Definition
fd.dusart.*_smpl_cfg.period
fd.dusart.*_sym_cfg.clk_high
fd.dusart.*_sym_cfg.clk_low
T
CLK
t
DV
x (N
t
t
S
A1
A1
+1) x ((N
data(n+1)
data(n+1)
2 x T
T
T
t
DS
CPU
CPU
Min
0
3
5
H
CPU
+ 5
+ 5
+1) + (N
t
t
DH
DI
(4 x T
L
CPU
+1))
11 February 2010
Max
13
13
) + 22
From eCOG1
From Ext. Host
From eCOG1
From eCOG1
From Ext. Host
From Ext. Host
Units
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns