MC68HC711KS2MFN4 Freescale Semiconductor, MC68HC711KS2MFN4 Datasheet - Page 102
MC68HC711KS2MFN4
Manufacturer Part Number
MC68HC711KS2MFN4
Description
32K EPROM - SLOW MODE
Manufacturer
Freescale Semiconductor
Datasheet
1.MC68HC711KS2MFN4.pdf
(290 pages)
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Operating Modes and On-Chip Memory
4.9 XOUT Pin Control
4.9.1 System Configuration Register
Technical Data
102
Address: $003F
The XOUT pin provides a buffered XTAL signal to synchronize external
devices with the MCU. It is enabled by the CLKX bit in the system
configuration (CONFIG) register. The frequency of XOUT can be divided
by one-of-four divisors selected by the XDV[1:0] bits in the system
configuration options 2 (OPT2) register. The XOUT pin is not configured
on all packages. Refer to the pin assignments in
Description.
Writable once in normal modes and writable at any time in special modes
CLKX — XOUT Clock Enable Bit
Reset:
Read:
Write:
The CLKX bit is a switch that enables a buffered clock running at the
same frequency as a referenced crystal. This buffered clock is
intended to synchronize external devices with the MCU.
0 = The XOUT pin is disabled.
1 = The X clock is driven out on the XOUT pin.
Figure 4-14. System Configuration Register (CONFIG)
ROMAD
Operating Modes and On-Chip Memory
Bit 7
—
6
1
1
CLKX
—
5
PAREN
—
4
NOSEC
3
1
NOCOP
Section 2. Pin
—
2
M68HC11K Family
ROMON
—
1
MOTOROLA
EEON
Bit 0
—
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