ispPAC-POWR6AT6-01SN32I Lattice, ispPAC-POWR6AT6-01SN32I Datasheet
ispPAC-POWR6AT6-01SN32I
Specifications of ispPAC-POWR6AT6-01SN32I
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ispPAC-POWR6AT6-01SN32I Summary of contents
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... The on-chip 10-bit A/D converter can both be used to monitor the V MON for implementing digital closed loop mode for maintain- ing the output voltage of all power supplies controlled by the monitoring and trimming section of the ispPAC- POWR6AT6 device. 2 The I C bus/SMBus interface allows an external micro- ...
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... Lattice Semiconductor Figure 3-1. ispPAC-POWR6AT6 Block Diagram VMON1 VMON1GS VMON2 VMON2GS VMON3 VMON3GS VMON4 VMON4GS VMON5 VMON5GS VMON6 VMON6GS SCL Interface SDA Decoder Set Point Registers ADC Control Logic OSC ispPAC-POWR6AT6 3-2 ispPAC-POWR6AT6 Data Sheet DAC TrimCell 1 DAC TrimCell 2 DAC TrimCell 3 ...
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... Programmable DAC Offset -320mV to +320mV from Programmable DAC Offset 3-3 ispPAC-POWR6AT6 Data Sheet Description Trim Select Input 0 Trim Select Input 1 Enables closed loop trim process (asserted low) Signals that all TrimCells selected for closed- loop trim have reached a trim locked condi- tion. Can be confi ...
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... GND pin. 4. VCCA and VCCD pins must be connected together on the circuit board. Pin Type Voltage Range 3-4 ispPAC-POWR6AT6 Data Sheet Description JTAG Test Data Out JTAG Test Clock Input JTAG Test Mode Select; Internal Pullup JTAG Test Data In ...
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... True for Vmon input voltage from 600mV to 2.048V. Values less than 600mV will see higher input impedance values. Parameter Conditions Parameter pins MON pins MONGS CLTLOCK/SMBA (Note 1) Power applied Conditions supplies. ) MON Conditions 1 Input mode = Attenuated Input mode = Unattenuated 3-5 ispPAC-POWR6AT6 Data Sheet Min. Max. -0.5 4.5 -0.5 4.5 -0.5 6 -0.5 6 -0.5 6 -0.5 6 -65 150 -65 125 Conditions Min ...
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... This is the total resultant error in the trimmed power supply output voltage referred to any DAC code due to the DAC’s INL, DNL, gain, out- put impedance, offset error and bipolar offset error across the industrial temperature range and the ispPAC-POWR6AT6 operating V and V ranges ...
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... CCJ VPS[0:1], TDI, TMS, CLTENb 3.3V CCD CCJ SCL, SDA TDI, TMS 2.5V CCJ I = 20mA SINK ; TDO, TDI, TMS referenced to V CCD Definition 3-7 ispPAC-POWR6AT6 Data Sheet Min. Typ. Max. +/-10 70 0.8 30% V 0.7 2.0 70 CCD CCD 1.7 0.8 . CCJ 100KHz 400KHz Min ...
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... VIL State Update-IR Conditions SU1 CKH Select-DR Scan SU1 H SU1 CKL PWP CKH Run-Test/Idle (Program) Select-DR Scan 3-8 ispPAC-POWR6AT6 Data Sheet Min. Typ. Max. 10 — — 30 — — 30 — — 200 — — — — 10 — — — — 10 — — 20 — ...
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... CKH CKL VIH TCK VIL State Update-IR Run-Test/Idle (Erase or Program SU1 PWV CKH Run-Test/Idle (Program) Select-DR Scan SU1 PWP CKH Select-DR Scan 3-9 ispPAC-POWR6AT6 Data Sheet SU1 H SU1 CKH CKL Update-IR t (Actual) HVDIS SU1 H SU1 H SU1 CKH CKL CKH PWV ...
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... Theory of Operation Voltage Measurement with the On-chip Analog to Digital Converter (ADC) The ispPAC-POWR6AT6 has an on-chip analog to digital converter that can be used for measuring the voltages at the VMON inputs. The ADC is also used in closed loop trimming of DC-DC converters. Close loop trimming is cov- ered later in this document ...
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... Controlling Power Supply Output Voltage with the Margin/ Trim Block One of the key features of the ispPAC-POWR6AT6 is its ability to make adjustments to the power supplies that it may also be monitoring. This is accomplished through the Trim and Margin Block of the device. The Trim and Mar- gin Block can adjust voltages six different power supplies through TrimCells as shown in Figure 3-7. The DC-DC blocks in the fi ...
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... CLTLOCK/SMBA Input From ADC Mux Read – 10-bit ADC Code There are six TrimCells in the ispPAC-POWR6AT6 device, enabling simultaneous control six individual power supplies. Each TrimCell can generate up to four trimming voltages to control the output voltage of the DC-DC converter. Figure 3-8. TrimCell Driving a Typical DC-DC Converter ...
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... The method to calculate the values of the resistors R1, R2, and R3 are described in a separate application note. Voltage Profile Control The Margin / Trim Block of ispPAC-POWR6AT6 consists of six TrimCells. Because all six TrimCells in the Margin / Trim Block are controlled by a common voltage profile control signals, they all operate at the same voltage profile. ...
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... This operation iterates until the setpoint and the DC-DC converter voltage are equal. Figure 3-10 shows the closed loop trim operation of a TrimCell. At regular intervals (as determined by the Update Rate Control register) the ispPAC-POWR6AT6 device initiates the closed loop power supply voltage correction cycle through the following blocks: • ...
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... The delay is the time required for ispPAC-POWR6AT6 control logic to complete a trim update cycle. Table 3-2 shows typical times for update cycles based on which of four trim rates is initially chosen in PAC-Designer. When the trim process is halted, it should also be noted the trim output DACs have constant voltage output levels (corresponding to their last input code setting). This condition can be safely maintained indefi ...
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... Otherwise, if control of when closed-loop trimming begins is not critical, the CLTENb pin can be tied to ground. This will cause closed-loop trim to begin immediately after the initial power on of the ispPAC-POWR6AT6 is completed. Closed Loop Trim Start-up Behavior The contents of the closed loop register, upon power-up, will contain a value 80h (Bipolar-zero) value ...
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... Each slave device on a given I C bus is assigned a unique address. The ispPAC-POWR6AT6 implements the 7-bit addressing portion of the standard. Any 7-bit address can be assigned to the ispPAC-POWR6AT6 device by pro- gramming through JTAG. When selecting a device address, one should note that several addresses are reserved ...
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... The second transaction performs the actual read. The first frame contains the 7-bit device address with the R/W bit held High. In the second frame the ispPAC- POWR6AT6 asserts data out on the bus in response to the SCL signal. Note that the acknowledge signal in the second frame is asserted by the master device and not the ispPAC-POWR6AT6 ...
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... CLTLOCK_status bit is set to a “1”. 2 The I C closed-loop trim register has one read/write bit (cltlock_status). When ispPAC-POWR6AT6 is configured in PAC-Designer to operate in SMBus Alert mode set to a “1” by device control logic to send an SMBus Alert. Logic then waits for acknowledged by a host I ...
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... C Closed Loop Trim Status Register 0x00 – CLTLOCK_STATUS (b6 = Read/Write; all others Read Only) X SMBA possible to read the value of the voltage present on any of the VMON inputs by using the ispPAC-POWR6AT6’s ADC. Three registers provide the I Figure 3-16. ADC Interface Registers 0x01 - ADC_VALUE_LOW (Read Only ...
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... UES30 The I C interface also provides the ability to initiate reset operations. The ispPAC-POWR6AT6 may be reset by issu- 2 ing a write of any value to the I C RESET register (Figure 3-18). Refer to the RESET Command via JTAG or I section of this data sheet for further information. note in specifications), the only way to insure a valid ADC ...
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... Figure 3-18 Reset Register 0x8 - RESET (Write Only The ispPAC-POWR6AT6 also provides the user with the ability to program the trim values over the I writing the appropriate binary word to the associated trim register (Figure 3-19). 2 Figure 3-19 Trim Registers 0x9 - TRIM1_TRIM (Read/Write) D7 ...
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... Determine “Lock” status of Trim-n The ispPAC-POWR6AT6 contains trim detection processing circuitry to signal when closed-loop trimming is com- plete for selected trim output pins. This signal is output on the closed-loop control output pin (CLTLOCK/SMBA) which has a open drain output and is normally asserted low (pull down). When all closed-loop trim output pins reach a completion or trim “ ...
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... The typical flow for an SMBAlert transaction is as follows (Figure 3-22 closed loop trim register SMBA bit is forced to high by internal ispPAC-POWR6AT6 control logic when- ever the trim lock status changes 2. ispPAC-POWR6AT6 closed-loop trim control logic pulls the CLTLOCK/SMBA pin low 3. Master responds to interrupt from SMBA line 4 ...
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... After CLTLOCK/SMBA has been released, the bus master (typically a microcontroller) may opt to perform some service functions in which it may send data to or read data from the ispPAC-POWR6AT6. As part of the service functions, the bus master will typically need to clear whatever condition initiated the SMBAlert request (power sup- ply malfunction, etc ...
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... It demonstrates proper layout techniques for the ispPAC-POWR1220AT8 which also apply to the ispPAC-POWR6AT6 and can be used in real time to check circuit operation as part of the design process. Input and output connections are provided to aid in the evaluation of either device for a given application. (Figure 3-24). ...
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... E CMOS cells these non-volatile cells that store the configuration or the ispPAC-POWR6AT6. A set of instruc- tions are defined that access all data registers and perform other internal control operations. For compatibility between compliant devices, two data registers are mandated by the IEEE 1149.1 specification. Others are func- tionally specifi ...
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... BYPASS and EXTEST instruction code patterns being specifically called out (all ones and all zeroes respec- tively). The ispPAC-POWR6AT6 contains the required minimum instruction set as well as one from the optional instruction set. In addition, there are several proprietary instructions that allow the device to be configured and ver- ifi ...
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... TDI and TDO. Again, since the ispPAC-POWR6AT6 has no boundary scan logic, the device is put in the BYPASS mode to ensure specification compatibility. The bit code of this instruction is defined by the 1149.1 standard to be all zeros (000000). ...
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... A brief description of each unique instruction is provided in detail below, and the bit codes are found in Table 3-7. BULK_ERASE - This instruction will bulk erase the ispPAC-POWR6AT6. The action occurs at the second rising edge of TCK in Run-Test-Idle JTAG state. The device must already be in programming mode (PROGRAM_ENABLE instruction) ...
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... Lattice Semiconductor RESET - This command resets the ispPAC-POWR6AT6 to a condition near that of the power-on reset state (refer to 2 reset command via JTAG section of this data sheet for more details and known exceptions). ERASE_DONE_BIT - This instruction erases the ispPAC-POWR6A6 DONE bit. CFG_VERIFY - This instruction is used to verify the contents of the selected configuration array column. This spe- cifi ...
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... FEATURE IS OPTIONAL. DIMENSION b APPLIES TO PLATED 4 TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.30 mm FROM TERMINAL TIP. APPLIES TO EXPOSED PORTION OF TERMINALS 0. 0. 32X E B 0.50 TYP VIEW A VIEW A 3-32 ispPAC-POWR6AT6 Data Sheet D2 PIN #1 ID FIDUCIAL LOCATED IN THIS AREA 0. BOTTOM VIEW SYMBOL MIN. NOM. ...
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... Use 32-pin QFNS package for all new designs. Refer to PCN #13A-08 for 32-pin QFN package discontinuance 4.75 5.00 L 32X 0. SYMBOL 3-33 ispPAC-POWR6AT6 Data Sheet PIN #1 ID FIDUCIAL LOCATED IN THIS ARE DIEPAD (EXPOSED BACKSIDE 3.5 4X BOTTOM VIEW MIN. NOM. MAX 0.85 1.00 ...
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... Part Number ispPAC-POWR6AT6-01S32I ispPAC-POWR6AT6-01N32I 1. Use QFNS package. QFN package devices have been discontinued via PCN #13A-08. Lead-Free Packaging Part Number ispPAC-POWR6AT6-01SN32I ispPAC-POWR6AT6-01NN32I 1. Use QFNS package. QFN package devices have been discontinued via PCN #13A-08. ispPAC-POWR6AT6 Data Sheet Operating Temperature Range I = Industrial (-40 ...
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... Increased Max DAC output current to +/- 200 µA. Included V and V specifications for References to Die Pad added to Pin Descriptions table, Recommended Operating Condi- tions table and Package Options diagram. Added 32-pin QFNS package Ordering Part Number information per PCN #13A-08. 3-35 ispPAC-POWR6AT6 Data Sheet VMON6GS 23 VMON5 22 VMON5GS 21 ...