ispPAC-POWR6AT6-01SN32I Lattice, ispPAC-POWR6AT6-01SN32I Datasheet - Page 30

• Manufacturer Part Number: ispPAC-POWR6AT6-01SN32I
• Description: Supervisory Circuits Prec Prog Pwr Supply Seq Mon Trim IND
• Manufacturer: Lattice
• Series: ispPAC®r

Specifications of ispPAC-POWR6AT6-01SN32I

• Number Of Voltages Monitored: 6
• Monitored Voltage: Adjustable
• Undervoltage Threshold: Adjustable
• Overvoltage Threshold: Adjustable
• Manual Reset: Not Resettable
• Watchdog: No Watchdog
• Supply Voltage (max): 3.96 V
• Supply Voltage (min): 2.8 V
• Supply Current (typ): 10000 uA
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: QFNS-32
• Minimum Operating Temperature: - 40 C
• Applications: Power Supply Controller/Monitor
• Voltage - Input: -0.3 V ~ 5.9 V
• Voltage - Supply: 2.8 V ~ 3.96 V
• Current - Supply: 10mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: *
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Lattice Semiconductor
Figure 3-27. ispPAC-POWR6AT6 ID Code
ispPAC-POWR6AT6 Specific Instructions
There are 15 unique instructions specified by Lattice for the ispPAC-POWR6AT6. These instructions are primarily
used to interface to the various user registers and the E
used to control or monitor other features of the device. A brief description of each unique instruction is provided in
detail below, and the bit codes are found in Table 3-7.
BULK_ERASE - This instruction will bulk erase the ispPAC-POWR6AT6. The action occurs at the second rising
edge of TCK in Run-Test-Idle JTAG state. The device must already be in programming mode
(PROGRAM_ENABLE instruction).
PROGRAM_SECURITY - This instruction is used to program the electronic security fuse (ESF) bit. Programming
the ESF bit protects proprietary designs from being read out. The programming occurs at the second rising edge of
the TCK in Run-Test-Idle JTAG state. The device must already be in programming mode (PROGRAM_ENABLE
instruction).
DISCHARGE - This instruction is used to discharge the internal programming supply voltage after an erase or pro-
gramming cycle and prepares ispPAC-POWR6AT6 for a read cycle.
PROGRAM_ENABLE - This instruction enables the programming mode of the ispPAC-POWR6AT6.
IDCODE - This instruction connects the output of the Identification Code Data Shift (IDCODE) Register to TDO
(Figure 3-28), to support reading out the identification code.
Figure 3-28. IDCODE Register
UES_READ - This instruction both reads the E
between the TDI and TDO pins (as shown in Figure 3-29), to support programming or reading of the user electronic
signature bits.
Figure 3-29. UES Register
UES_PROG - This instruction will program the content of the UES Register into the UES E
device must already be in programming mode (PROGRAM_ ENABLE instruction).
PROGRAM_DISABLE - This instruction disables the programming mode of the ispPAC-POWR6A6. The Test-
Logic-Reset JTAG state can also be used to cancel the programming mode of the ispPAC-POWR6A6.
Bit
Bit
31
15
Bit
30
Bit
14
Bit
29
Bit
13
E
2
XXXX / 0000 0001 1000 0000 / 0000 0100 001 / 1
MSB
Configured
Bit
28
Bit
12
Version
(4 bits)
0180h = ispPAC-POWR6AT6
Bit
Bit
27
11
Part Number
(16 bits)
2
CMOS bits in the UES register and places the UES register
3-30
2
CMOS non-volatile memory. Additional instructions are
Lattice Semiconductor
JEDEC Manufacturer
Identity Code for
(11 bits)
Bit
Bit
4
4
Bit
Bit
per 1149.1-1990
3
3
ispPAC-POWR6AT6 Data Sheet
Constant 1
LSB
(1 bit)
Bit
Bit
2
2
Bit
Bit
1
1
2
CMOS memory. The
Bit
Bit
0
0
TDO
TDO