PEB3081FV14XT Lantiq, PEB3081FV14XT Datasheet - Page 48

• Manufacturer Part Number: PEB3081FV14XT
• Manufacturer: Lantiq

Specifications of PEB3081FV14XT

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Compliant

PEB 3081
PEF 3081
Description of Functional Blocks
Preliminary
3.3.5
Receiver Characteristics
The receiver consists of a differential input stage, a peak detector and a set of
comparators. Additional noise immunity is achieved by digital oversampling after the
comparators. A simplified equivalent circuit of the receiver is shown in
Figure
22.
100 kOhm
Figure 22
Equivalent Internal Circuit of the Receiver Stage
The input stage works together with external 10 k
resistors to match the input voltage
to the internal thresholds. The data detection threshold Vref is continuously adapted
between a maximal (Vrefmax) and a minimal (Vrefmin) reference level related to the line
level. The peak detector requires maximum 2 s to reach the peak value while storing
the peak level for at least 250 s (RC > 1 ms).
The additional level detector for power up/down control works with a fixed threshold
VrefLD. The level detector monitors the line input signals to detect whether an INFO is
present. When closing an analog loop it is therefore possible to indicate an incoming
signal during activated loop.
Data Sheet
48
2000-09-27