PEB3081FV14XT Lantiq, PEB3081FV14XT Datasheet - Page 88
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PEB3081FV14XT
Manufacturer Part Number
PEB3081FV14XT
Description
Manufacturer
Lantiq
Datasheet
1.PEB3081FV14XT.pdf
(198 pages)
Specifications of PEB3081FV14XT
Number Of Line Interfaces
1
Control Interface
HDLC
Lead Free Status / Rohs Status
Compliant
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Preliminary
.
Figure 43
Looping and Shifting Data
Figure 44
configuration possibilities with the bits TSS, DPS, EN and SWAP in the registers
TSDPxy or CDAx_CR:
a) looping IOM-2 time slot data from DU to DD or vice versa (SWAP = 0)
b) shifting data from TSa to TSb and TSc to TSd in both transmission directions (SWAP
= 1)
c) switching data from TSa to TSb and looping from DU to DD or TSc to TSd and looping
from DD to DU respectively
TSa is programmed in TSDP10, TSb in TSDP11, TSc in TSDP20 and TSd in TSDP21.
It should also be noted that the input control of CDA registers is swapped if SWAP=1
while the output control is not affected (e.g. for CDA11 in example a: EN_I1=1 and
EN_O1=1, whereas for CDA11 in example b: EN_I0=1 and EN_O1=1).
Data Sheet
*) In the normal mode (SWAP=0) the input of CDAx0 and CDAx1 is enabled via EN_I0 and
EN_I1, respectively. If SWAP=1 EN_I0 controls the input of CDAx1 and EN_I1 controls the
input of CDAx0. The output control (EN_O0 and EN_O1) is not affected by SWAP.
x = 1 or 2; a,b = 0...31
gives examples for typical configurations with the above explained control and
Data Access via CDAx1 and CDAx2 register pairs
(EN_O0)
1
output
CDAx0
Enable
TSa
1
0
TSa
input *
(EN_I0)
0
1
1
1
CDA_CRx
Register
Control
88
(SWAP)
Input
Swap
Description of Functional Blocks
1
(EN_I1)
1
input *
CDAx1
1
TSb
0
TSb
Enable
0
1
(EN_O1)
output
1
PEB 3081
PEF 3081
2000-09-27
IOM_HAND.FM4
DD
DU
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