PEB24901HV12 Lantiq, PEB24901HV12 Datasheet - Page 17

• Manufacturer Part Number: PEB24901HV12
• Manufacturer: Lantiq

Specifications of PEB24901HV12

• Lead Free Status / Rohs Status: Supplier Unconfirmed

Semiconductor Group
3
3.1
In the exchange (LT mode) , all timing signals are derived from a system clock via the
PLL internal to the PEB 24902 Quad IEC AFE.
The master clock is generated with a crystal oscillator connected to the Quad IEC AFE.
It is synchronised to the system clock (8 kHz, 512 kHz or 2048 kHz) with the PLL of the
Quad IEC AFE.
Master clock nominal frequency:
Max. Difference of phase deviations of Master clock and FSC:
Max. low freq. phase wander within 1 period:
Jitter (peak-to-peak):
The jitter on the 15.36 MHz master clock is passed to the U-interface without change.
Hence, fig. 4 reflects the jitter as given in FTZ 1 TR 220.
Figure 4: Maximum Clock Jitter
3.2
3.2.1 IOM-2 System Interface
The PEB 24901 Quad IEC DFE-T is equipped with a second generation digital ISDN
Oriented Modular (IOM-2) interface, for communication with upper layer functions, such
as IDEC
represent the first switching stage towards the exchange system.
Application Guide
Clock Generation
Interfaces
®
(PEB 2075), EPIC
UI (15.36 MHz)
3.2
32
®
(PEB 2055) and ELIC
3
jitter frequency (Hz)
16
30
®
(PEB 20550). EPIC and ELIC
15.36 MHz
see figure 4
60000
18 s
0.85 ps
PEB 24901
02.95