PEF24911HV22XP Lantiq, PEF24911HV22XP Datasheet - Page 4
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PEF24911HV22XP
Manufacturer Part Number
PEF24911HV22XP
Description
Manufacturer
Lantiq
Datasheet
1.PEF24911HV22XP.pdf
(155 pages)
Specifications of PEF24911HV22XP
Control Interface
HDLC
Lead Free Status / Rohs Status
Supplier Unconfirmed
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PEF 24911
Revision History:
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For questions on technology, delivery and prices please contact the Infineon
Technologies Offices in Germany or the Infineon Technologies Companies and
Representatives worldwide: see our webpage at http://www.infineon.com
13,
Subjects (major changes since last revision)
New function: Disable Super Frame Marker introduced on pin 16: DSFM
Refined description of pin 49: CRCON
Especially, CRCON = ’1’ selects MFILT= 0011 0xxx (erroneously, MFILT=
000010xx was documented in DS2)
Added note: MON-12 read access is impossible in state ’Deactivated’
Restriction: PACA/PACE must not be used during local loopback active
C/I-command LTD added (function as in V1.x)
AR0 and ARX set UOA = ’1’ (before: AR0 and ARX set UOA to the same
value as the received SAI bit)
Refined description ’Framer / Deframer Loopback’:
- always transparent
- prerequisite is transparent state
Bit Error Rate Counter: refined operational description
Data Through is only test mode, C/I-command = ARL must not be applied
when pin DT = ’1’
Refined description of ’Control via MON-2’
Removed ’Propagation Delay Measurement’: function not supported
Refined description of mode register evaluation timing
Removed description OPMODE.MODE1,0: no settings possible
SAI-evaluation / UOA-control:
- M4RMASK.bit6: only SAI-reporting via MON-2 is selected
- M4WMASK.bit6: in addition to UOA-bit control, also SAI-evaluation by the
state machine is selected; refined description
(see also
Changed TEST.bit6 = ’1’ (not ’0’)
Statemachine is put into transparent state by TRANS=’0’ (not ’1’)
Refined reset timing description; added 900µs internal delay to figure
Refined description of FSC / Superframe-FSC-timing
Removed input capacitance of pin XIN (pin XIN is not supported)
Table
21: Max. connection resistance specified
Figure 21
2001-07-16
Data Sheet 11.00
and
Figure
22)
DS 3
DS 2
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