DS1248Y-70+ Dallas Semiconductor, DS1248Y-70+ Datasheet - Page 8

• Manufacturer Part Number: DS1248Y-70+
• Description: PHNTHM RTC MOD 128K X 8 70NS
• Manufacturer: Dallas Semiconductor

Specifications of DS1248Y-70+

• Capacitance, Input: 5 pF
• Capacitance, Output: 5 pF
• Current, Input, Leakage: ±1 μA
• Current, Operating: 85 mA
• Current, Output, Leakage: ±1
• Data Retention: 10 yrs.
• Density: 1024K
• Interface: Parallel Bus
• Memory Type: Non-Volatile SRAM
• Organization: 128K×8
• Package Type: EDIP
• Temperature, Operating: 0 to +70 °C
• Time, Access: 70 ns
• Time, Address Hold: 5
• Time, Fall: 5 ns
• Time, Rise: 5 ns
• Voltage, Input, High: 5.3 V
• Voltage, Input, Low: 0.8 V
• Voltage, Supply: 5 V
• Lead Free Status / Rohs Status: RoHS Compliant part

AC TEST CONDITIONS
Output Load: 50pF + 1TTL Gate
Input Pulse Levels: 0 to 3V
Timing Measurement Reference Levels
Input Pulse Rise and Fall Times: 5ns
NOTES:
1) WE is high for a read cycle.
2) OE = V
3) t
4) t
5) These parameters are sampled with a 50pF load and are not 100% tested.
6) If the CE low transition occurs simultaneously with or later than the WE low transition in Write Cycle
7) If the CE high transition occurs prior to or simultaneously with the WE high transition, the output
8) If WE is low or the WE low transition occurs prior to or simultaneously with the CE low transition,
9) The expected t
10) t
11) Voltages are referenced to ground.
12) RST (Pin 1) has an internal pullup resistor.
13) RTC modules can be successfully processed through conventional wave-soldering techniques as long
Output: 1.5V
Input: 1.5V
low to the earlier of CE or WE going high.
1, the output buffers remain in a high-impedance state during this period.
buffers remain in a high-impedance state during this period.
the output buffers remain in a high impedance state during this period.
running.
as temperature exposure to the lithium energy source contained within does not exceed +85°C. Post-
solder cleaning with water-washing techniques is acceptable, provided that ultrasonic vibration is not
used. See the PowerCap package drawing for details regarding the PowerCap package.
WP
DH
WR
, t
is specified as the logical AND of CE and WE. t
is a function of the latter occurring edge of WE or CE .
DS
IH
are measured from the earlier of CE or WE going high.
or V
IL
DR
. If CE = V
is defined as cumulative time in the absence of V
IH
during write cycle, the output buffers remain in a high impedance state.
17 of 18
WP
is measured from the latter of CE or WE going
CC
with the clock oscillator