MT8HTF12864HTY-667E1 Micron Technology Inc, MT8HTF12864HTY-667E1 Datasheet - Page 13
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MT8HTF12864HTY-667E1
Manufacturer Part Number
MT8HTF12864HTY-667E1
Description
Manufacturer
Micron Technology Inc
Datasheet
1.MT8HTF12864HTY-667E1.pdf
(19 pages)
Specifications of MT8HTF12864HTY-667E1
Main Category
DRAM Module
Sub-category
DDR2 SDRAM
Module Type
200SODIMM
Device Core Size
64b
Organization
128Mx64
Total Density
1GByte
Chip Density
1Gb
Maximum Clock Rate
667MHz
Operating Supply Voltage (typ)
1.8V
Operating Current
900mA
Number Of Elements
8
Operating Supply Voltage (max)
1.9V
Operating Supply Voltage (min)
1.7V
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Pin Count
200
Mounting
Socket
Lead Free Status / Rohs Status
Compliant
Table 11: DDR2 I
Values shown for MT47H32M16 DDR2 SDRAM only and are computed from values specified in the 512Mb (32 Meg x 16)
component data sheet
PDF: 09005aef80ebed66
htf8c32_64_128x64hd.pdf - Rev. E 3/10 EN
Parameter
Operating one bank active-precharge current:
t
commands; Address bus inputs are switching; Data bus inputs are switching
Operating one bank active-read-precharge current: I
4, CL = CL (I
(I
Address bus inputs are switching; Data pattern is same as I
Precharge power-down current: All device banks idle;
CKE is LOW; Other control and address bus inputs are stable; Data bus in-
puts are floating
Precharge quiet standby current: All device banks idle;
CKE is HIGH, S# is HIGH; Other control and address bus inputs are stable;
Data bus inputs are floating
Precharge standby current: All device banks idle;
HIGH, S# is HIGH; Other control and address bus inputs are switching; Da-
ta bus inputs are switching
Active power-down current: All device banks open;
=
puts are stable; Data bus inputs are floating
Active standby current: All device banks open;
t
mands; Other control and address bus inputs are switching; Data bus
inputs are switching
Operating burst write current: All device banks open; Continuous
burst writes; BL = 4, CL = CL (I
(I
Address bus inputs are switching; Data bus inputs are switching
Operating burst read current: All device banks open; Continuous burst
read, I
MAX (I
mands; Address bus inputs are switching; Data bus inputs are switching
Burst refresh current:
(I
trol and address bus inputs are switching; Data bus inputs are switching
Self refresh current: CK and CK# at 0V; CKE ≤ 0.2V; Other control and
address bus inputs are floating; Data bus inputs are floating
RC (I
RAS MAX (I
DD
DD
DD
t
CK (I
),
),
) interval; CKE is HIGH, S# is HIGH between valid commands; Other con-
DD
t
t
RCD =
RP =
OUT
DD
DD
),
),
t
); CKE is LOW; Other control and address bus in-
RAS =
= 0mA; BL = 4, CL = CL (I
t
t
DD
RP (I
RP =
DD
t
RCD (I
), AL = 0;
),
t
DD
t
t
RP =
RAS MIN (I
RP (I
); CKE is HIGH, S# is HIGH between valid commands;
DD
DD
DD
); CKE is HIGH, S# is HIGH between valid commands;
t
RP (I
Specifications and Conditions – 512MB
t
CK =
t
); CKE is HIGH, S# is HIGH between valid com-
CK =
DD
DD
t
); CKE is HIGH, S# is HIGH between valid com-
DD
CK (I
t
); CKE is HIGH, S# is HIGH between valid
CK (I
), AL = 0;
DD
DD
DD
),
), AL = 0;
); REFRESH command at every
t
RC =
t
CK =
t
256MB, 512MB, 1GB (x64, DR) 200-Pin DDR2 SODIMM
RC (I
t
CK =
t
CK (I
DD
t
CK =
t
CK =
),
t
t
DD
CK (I
CK =
t
RAS =
),
t
CK
t
CK (I
t
t
RAS =
DD
CK (I
t
OUT
CK =
t
DD4W
t
CK (I
CK =
),
13
Fast PDN exit
MR[12] = 0
Slow PDN exit
MR[12] = 1
t
DD
RAS MIN
t
= 0mA; BL =
DD
RAS =
),
t
DD
t
CK (I
RAS MAX
),
t
t
CK (I
); CKE is
RAS =
t
RC =
t
RFC
t
DD
RAS
DD
Micron Technology, Inc. reserves the right to change products or specifications without notice.
);
);
Symbol
I
I
I
I
I
I
I
DD4W
I
I
DD2Q
I
I
DD2N
DD3N
DD4R
DD2P
DD3P
DD0
DD1
DD5
DD6
1
1
2
2
2
2
1
2
2
2
1
-80E/-
1200
1120
1840
800
560
680
520
560
320
600
56
96
56
1020
1480
-667
500
620
440
480
280
560
960
© 2006 Micron Technology, Inc. All rights reserved.
56
96
56
I
DD
1400
-53E
Specifications
460
560
360
400
240
480
840
800
56
96
56
-40E
1360
440
520
320
360
200
400
640
620
56
96
56
Units
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA