MT46H8M32LFB5-75 IT:A Micron Technology Inc, MT46H8M32LFB5-75 IT:A Datasheet - Page 75
MT46H8M32LFB5-75 IT:A
Manufacturer Part Number
MT46H8M32LFB5-75 IT:A
Description
Manufacturer
Micron Technology Inc
Type
DDR SDRAMr
Datasheet
1.MT46H8M32LFB5-75_ITA.pdf
(96 pages)
Specifications of MT46H8M32LFB5-75 IT:A
Organization
8Mx32
Density
256Mb
Address Bus
14b
Access Time (max)
6.5/6ns
Maximum Clock Rate
133MHz
Operating Supply Voltage (typ)
1.8V
Package Type
VFBGA
Operating Temp Range
-40C to 85C
Operating Supply Voltage (max)
1.95V
Operating Supply Voltage (min)
1.7V
Supply Current
120mA
Pin Count
90
Mounting
Surface Mount
Operating Temperature Classification
Industrial
Lead Free Status / Rohs Status
Compliant
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Figure 38: WRITE-to-READ – Uninterrupting
PDF: 09005aef834bf85b
256mb_mobile_ddr_sdram_t36n.pdf - Rev. H 11/09 EN
Command
Address
t
t
t
DQSSnom
DQSSmin
DQSSmax
DQS
DQ
DQS
DQ
DQS
DQ
CK#
DM
DM
DM
CK
5
5
5
1
WRITE
Bank a,
Col b
T0
Notes:
t
t
2,3
t
DQSS
DQSS
DQSS
1. The READ and WRITE commands are to the same device. However, the READ and WRITE
2. A10 is LOW with the WRITE command (auto precharge is disabled).
3. An uninterrupted burst of 4 is shown.
4.
5. D
D
IN
commands may be to different devices, in which case
READ command could be applied earlier.
t
WTR is referenced from the first positive CK edge after the last data-in pair.
NOP
D
IN
T1
IN
b = data-in for column b; D
D
D
IN
IN
T1n
D
IN
D
D
IN
IN
NOP
D
T2
IN
D
D
IN
IN
D
T2n
IN
75
D
IN
NOP
T3
OUT
256Mb: x16, x32 Mobile LPDDR SDRAM
t
WTR
n = data-out for column n.
Micron Technology, Inc. reserves the right to change products or specifications without notice.
4
Bank a,
READ
Col n
T4
Don’t Care
t
WTR is not required and the
CL = 2
CL = 2
CL = 2
T5
NOP
©2008 Micron Technology, Inc. All rights reserved.
WRITE Operation
T5n
Transitioning Data
D
D
D
OUT
OUT
OUT
T6
NOP
D
D
D
OUT
OUT
OUT
T6n
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