W9751G6IB-3 Winbond Electronics, W9751G6IB-3 Datasheet - Page 31

• Manufacturer Part Number: W9751G6IB-3
• Manufacturer: Winbond Electronics
• Type: DDR2 SDRAMr

Specifications of W9751G6IB-3

• Organization: 32Mx16
• Density: 512Mb
• Address Bus: 15b
• Access Time (max): 450ps
• Maximum Clock Rate: 667MHz
• Operating Supply Voltage (typ): 1.8V
• Package Type: WBGA
• Operating Temp Range: 0C to 85C
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Supply Current: 160mA
• Pin Count: 84
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Compliant

8. OPERATION MODE
8.1
Notes:
1. All DDR2 SDRAM commands are defined by states of CS , RAS , CAS , WE and CKE at the rising edge of the clock.
2. Bank addresses BA[1:0] determine which bank is to be operated upon. For (E)MRS BA selects an (Extended) Mode Register.
3. Burst reads or writes at BL = 4 can not be terminated or interrupted. See Burst Interrupt in section 7.5 for details.
4. V
5. Self Refresh Exit is asynchronous.
6. The Power Down does not perform any refresh operations. The duration of Power Down Mode is therefore limited by the
Self Refresh Exit
Device Deselect
Write with Auto-
Read with Auto-
Mode Register
Bank Activate
Precharge All
No Operation
refresh requirements outlined in section 7.9.
Power Down
Power Down
Self Refresh
COMMAND
Single Bank
Mode Entry
(Extended)
Precharge
REF
precharge
precharge
Mode Exit
Refresh
Banks
Write
Read
Entry
Set
Command Truth Table
must be maintained during Self Refresh operation.
Previous
Cycle
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
CKE
Current
Cycle
H
H
H
H
H
H
H
H
X
X
H
H
H
L
L
BA1
BA0
BA
BA
BA
BA
BA
BA
BA
X
X
X
X
X
X
X
X
Column
Column
Column
Column
A12
A11
X
X
X
X
X
X
X
X
X
Row Address
- 31 -
OP Code
A10
H
H
H
X
X
X
X
X
X
X
L
L
L
Column
Column
Column
Column
A9-A0
X
X
X
X
X
X
X
X
X
Publication Release Date: Oct. 23, 2009
CS
H
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
RAS
H
H
H
H
H
X
X
H
X
H
X
H
L
L
L
L
L
L
W9751G6IB
CAS
H
H
H
H
X
X
H
X
H
X
H
L
L
L
L
L
L
L
WE
H
H
H
H
X
H
H
X
H
X
H
X
H
L
L
L
L
L
Revision A06
NOTES
1,2,3
1,2,3
1,2,3
1,2,3
1,4,5
1,2
1,2
1,2
1,4
1,6
1,6
1
1
1
1