LAN8187I-JT SMSC, LAN8187I-JT Datasheet - Page 15

• Manufacturer Part Number: LAN8187I-JT
• Description: TXRX ETHERNET 10/100 ESD PROT
• Manufacturer: SMSC
• Type: Transceiverr

Specifications of LAN8187I-JT

• Protocol: Ethernet
• Voltage - Supply: 1.6 V ~ 3.6 V
• Mounting Type: Surface Mount
• Package / Case: 64-TQFP, 64-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Drivers/receivers: -
• Other names: Q4223799

±15kV ESD Protected MII/RMII 10/100 Ethernet Transceiver with HP Auto-MDIX & flexPWR
Datasheet
SMSC LAN8187/LAN8187i
a.On nRST transition high, the PHY latches the state of the configuration pins in this table.
SIGNAL NAME
CH_SELECT
GPO0/RMII
AMDIX_EN
REG_EN
MODE2
MODE1
MODE0
Table 3.4 Boot Strap Configuration Inputs
TYPE
I/O
I
I
I
I
I
I
DATASHEET
PHY Operating Mode Bit 2: set the default MODE of the PHY.
See
the MODE options.
PHY Operating Mode Bit 1: set the default MODE of the PHY.
See
the MODE options.
PHY Operating Mode Bit 0: set the default MODE of the PHY.
See
the MODE options.
Regulator Enable: Internal +1.8V regulator enable:
VDDIO – Enables internal regulator.
VSS– Disables internal regulator.
As described in
power-on sequence to determine if the internal regulator should
turn on. When the regulator is disabled, external 1.8V must be
supplied to VDD_CORE, and the voltage at VDD33 must be at
least 2.64V before voltage is applied to VDD_CORE.
HP Auto-MDIX Enable: This pin is used to manualy disable the
HP Auto-MDIX function. This can be bypassed using the internal
register 27 bit 15. Please see
page 30
(VDDIO or Floating) – Enables HP Auto-MDIX.
VSS – Disables HP Auto-MDIX
Channel Select: This pin is used in conjunction with the
AMDIX_EN pin above to manualy select the channel to transmit
and receive on. For more information please see
“Auto-MDIX Control,” on page 30
(VDDIO or Floating) – MDIX - TX pair receives RX pair transmits.
0V – MDI -TX pair transmits RX pair receives.
General Purpose Output 0 – General Purpose Output signal.
Driven by bits in registers 27 and 31.
RMII – MII/RMII mode selection is latched on the rising edge of
the internal reset (nreset) based on the following strapping:
Float the GPO0 pin for MII mode or pull-high with an external
Pull-up resistor (see
Resistors,” on page
mode.
Note:
Section 5.4.9.2, "Mode Bus – MODE[2:0]," on page
Section 5.4.9.2, "Mode Bus – MODE[2:0]," on page
Section 5.4.9.2, "Mode Bus – MODE[2:0]," on page
15
for more information.
See
page 26
TM
Technology
Section 4.6.3, "MII vs. RMII Configuration," on
Section
for more details.
33) to VDDIO to set the device in RMII
Table 4.4, “Boot Strapping Configuration
4.9, this pin is sampled during the
DESCRIPTION
a
Table 4.3, “Auto-MDIX Control,” on
Revision 1.5 (01-10-08)
Table 4.3,
53, for
53, for
53, for