SI3019-F-FTR Silicon Laboratories Inc, SI3019-F-FTR Datasheet
SI3019-F-FTR
Specifications of SI3019-F-FTR
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SI3019-F-FTR Summary of contents
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Features PCM highway data interface µ-law/A-law companding SPI control interface GCI interface dynamic range TX/RX Line voltage monitor ...
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Si3050 + Si3018/19 2 Rev. 1.31 ...
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T C ABLE O F ONTENTS Section 1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Si3050 + Si3018/19 5.37. Companding in GCI Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Electrical Specifications Table 1. Recommended Operating Conditions and Thermal Information 1 Parameter Ambient Temperature Si3050 Supply Voltage, Digital 3 Thermal Resistance (Si3018/19) 3 Thermal Resistance (Si3050) Notes: 1. The Si3050 specifications are guaranteed when the typical application circuit (including ...
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Si3050 + Si3018/19 Table 2. Loop Characteristics = = (V 3 °C for K-Grade, see Figure 1 on page Parameter Symbol DC Termination Voltage DC Termination Voltage DC Termination Voltage ...
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Table 3. DC Characteristics 3 °C for F/K-Grade Parameter 1 High Level Input Voltage 1 Low Level Input Voltage High Level Output Voltage Low Level Output ...
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Si3050 + Si3018/19 Table 4. AC Characteristics = = (V 3 °C for F/K-Grade Parameter Sample Rate PCLK Input Frequency Receive Frequency Response Receive Frequency Response 1 Transmit Full-Scale Level 1,3 ...
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Table 4. AC Characteristics (Continued 3 °C for F/K-Grade Parameter 8 Dynamic Range (Caller ID mode) 8 Caller ID Full-Scale Level 6,9 Gain Accuracy 10 Transhybrid Balance 10 ...
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Si3050 + Si3018/19 Table 6. Switching Characteristics—General Inputs = = (V 3 °C for K-Grade Parameter Cycle Time, PCLK PCLK Duty Cycle PCLK Jitter Tolerance Rise Time, PCLK Fall ...
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Table 7. Switching Characteristics—Serial Peripheral Interface = = (V 3 °C for K-Grade Parameter* Cycle Time SCLK Rise Time, SCLK Fall Time, SCLK Delay Time, SCLK Fall to SDO Active ...
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Si3050 + Si3018/19 Table 8. Switching Characteristics—PCM Highway Serial Interface = = (V 3 °C for K-Grade Parameter Cycle Time PCLK Valid PCLK Inputs 2 FSYNC Period PCLK Duty ...
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Table 9. Switching Characteristics—GCI Highway Serial Interface = = (V 3 °C for K-Grade Parameter Cycle Time PCLK (Single Clocking Mode) Cycle Time PCLK (Double Clocking Mode) Valid PCLK ...
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Si3050 + Si3018/19 PCLK FSYNC DRX DTX Figure 6. GCI Highway Interface Timing Diagram (2x PCLK Mode) Table 10. Digital FIR Filter Characteristics—Transmit and Receive = = (V 3.0 to 3.6 V, Sample Rate 8 kHz Parameter Passband ...
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Figure 7. FIR Receive Filter Response Figure 8. FIR Receive Filter Passband Ripple For Figures 7–10, all filter plots apply to a sample rate kHz. For Figures 11–14, all filter plots apply to a sample rate ...
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Si3050 + Si3018/19 Figure 11. IIR Receive Filter Response Figure 12. IIR Receive Filter Passband Ripple Figure 13. IIR Transmit Filter Response 16 Figure 14. IIR Transmit Filter Passband Ripple Figure 15. IIR Receive Group Delay Figure 16. IIR Transmit ...
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Typical Application Schematic Si3050 + Si3018/19 Rev. 1.31 17 ...
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Si3050 + Si3018/19 3. Bill of Materials Component C1 C5, C6, C50, C51 C7 C8, C9 C10 1 C30, C31 2 D1, D2 Dual Diode, 225 mA, 300 V, (CMPD2004S) FB1, FB2 Q1 Q4, ...
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AOUT PWM Output Figure 18 illustrates an optional circuit to support the pulse width modulation (PWM) output capability of the Si3050 for call progress monitoring purposes.To enable this mode, the INTE bit (Register 2) should be set to 0, ...
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... Four selectable ac terminations to increase return loss and trans-hybrid loss performance. +6 dBm TX/RX level mode (600 ) 5.1.2. Si3019 Globally-compliant, enhanced features line-side device—targets global DAA requirements for voice applications. Selectable dc terminations ...
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Table 13. Country Specific Register Settings Register 16 31 Country OHS OHS2 Argentina 0 1 Australia 1 Austria 0 Bahrain 0 Belgium 0 Brazil 0 Bulgaria 0 Canada 0 Chile 0 China 0 Colombia 0 Croatia 0 Cyprus 0 Czech ...
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Si3050 + Si3018/19 Table 13. Country Specific Register Settings (Continued) Register 16 Country OHS Ireland 0 Israel 0 Italy 0 Japan 0 Jordan 0 Kazakhstan 0 Kuwait 0 Latvia 0 Lebanon 0 Luxembourg 0 Macao 0 2 Malaysia 0 Malta ...
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Table 13. Country Specific Register Settings (Continued) Register 16 31 Country OHS OHS2 Slovakia 0 Slovenia 0 South Africa 0 South Korea 0 Spain 0 Sweden 0 Switzerland 0 Taiwan 0 3 TBR21 0 Thailand 0 UAE 0 United Kingdom ...
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... Si3050 and the telephone line. The Si3050 supplies power over the patented isolation capacitor link between the two devices, allowing the Si3019 to communicate with the Si3050 while on-hook and perform other on-hook functions, such as line voltage monitoring. When off-hook, the Si3018/19 also derives power from the line current supplied from the telephone line ...
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Calibration The Si3050 initiates two auto-calibrations by default when the device goes off-hook or experiences a loss of line power resistor calibration is performed to allow circuitry internal to the DAA to adjust to the exact ...
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... DODM bit is set) indicating that the line-derived power supply has collapsed. With the Si3019 line side, the LVS bits also can be read when on- or off-hook to determine the line voltage. Significant drops in line voltage can signal a parallel handset ...
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... Line Voltage Measurement (Si3019 Line Side Only) The Si3050 reports line voltage with the LVS[7:0] bits (Register 29) in both on- and off-hook states with a resolution per bit. The accuracy of these bits is approximately ±10%. Bits 0 through 7 of this 8-bit signed number indicate the value of the line voltage in 2s complement format ...
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Si3050 + Si3018/19 5.12.2. Loop Current Measurement When the Si3050 is off-hook, the LCS[4:0] bits measure loop current in 3.3 mA/bit resolution. With the LCS[4:0] bits, a user can detect another phone going off-hook by monitoring the dc loop current. ...
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... Register 3 and bit 1 in Register 44 can be set to enable hardware interrupt sources (bit 0 is available with the Venkel, SMEC, Si3019 line-side only). When one or more of these bits Panasonic is set, the AOUT/INT pin goes into an active state and stays active until the interrupts are serviced. If more ...
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... The Si3019 provides sixteen impedances when used with the Si3050. The ACIM[3:0] bits in Register 30 are used to select the ac impedance setting on the Si3019. The sixteen available settings for the Si3019 are listed in Table 17. The most widely used ac terminations are available as register options to satisfy requirements. The real 600 ...
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... For each of the sixteen ac termination settings, the programmable digital hybrid can be used to further reduce near-end echo. See "5.28. Transhybrid Balance" on page 37 for details. Table 17. AC Termination Settings for the Si3019 Line-Side Device ACIM[3:0] AC Termination 600 0000 900 0001 270 ...
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Si3050 + Si3018/19 The RDT behavior is also based on the RNG1-RNG2 voltage. When the RFWE bit positive ring signal sets the RDT bit for a period of time. When the RFWE bit positive ...
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... ROVM and INTE bits. Certain events such as billing tones can be sufficiently large to disrupt the line-derived power supply of the Voice DAA line side device (Si3018 or Si3019.) To ensure that the device maintains the off-hook line state during these events, the BTE bit should be set. If such an event occurs while the BTE bit is set, the BTD and BTDI bits will be asserted ...
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... Enable full wave rectified ring detection (RFWE, Register 18, bit 1). 2. Monitor the RDTP and RDTN register bits (or the POLI bit with the Si3019 line-side) to identify if a polarity reversal or a ring signal has occurred. A polarity reversal trips either the RDTP or RDTN ring ...
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... RNG 1/2 pins and presented to the host via the DTX pin. 4. Clear the ONHM bit after the caller ID data is received. 5.25.2. Type II Caller ID (Si3019 Line-Side Device Only) Type II Caller ID sends the CID data while the phone is off-hook. This mode is often referred to as caller ID/ call waiting (CID/CW) ...
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... After allowing the off-hook counter to expire (8 ms), normal transmission and reception can continue. If CID data reception is required, send the appropriate signal to the CO at this time. Figure 24. Implementing Type II Caller ID on the Si3050+Si3019 5.26. Overload Detection The Si3050 can be programmed to detect an overload condition that exceeds the normal operating power range of the DAA circuit ...
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To Link Si3050 Figure 25. Si3018/19 Signal Flow Diagram DRX TXG3 TXG2 TXA3 1 dB 0.1 dB Gain Gain/ATT Steps Steps 1 dB 0.1 dB Attenuation Gain/ATT Steps Steps IIRE DTX RXG3 Digital RXA2 RXA3 Filter Figure 26. Si3050 Signal ...
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Si3050 + Si3018/19 The PLL clock synthesizer settles quickly after powerup. However, the settling time depends on the PCLK frequency and it can be approximately predicted by the following equation 64/F settle PCLK For all valid PCLK frequencies ...
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Table 20. Pin Functionality in PCM or GCI Highway Mode Pin Name SDI_THRU SPI Data Throughput pin for Daisy Chaining Operation (Connects to the SDI pin of the subsequent device in the daisy chain) SCLK SDI SDO CS FSYNC PCLK ...
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Si3050 + Si3018/19 PCLK FSYNC PCLK_CNT DRX MSB DTX HI-Z MSB Figure 28. PCM Highway Transmission, Short FSYNC, Single Clock Cycle Delayed Transmission ...
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PCLK FSYNC PCLK_CNT DRX DTX HI-Z Figure 30. PCM Highway Transmission, Long FSYNC, Delayed Data Transfer PCLK FSYNC PCLK_CNT DRX M SB DTX HI Figure 31. PCM Highway Double Clocked Transmission, ...
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Si3050 + Si3018/19 5.33. Companding in PCM Mode The Si3050 supports both µ-Law companding formats in addition to 16-bit linear data. The 8-bit companding schemes follow a segmented curve formatted as a sign bit, three chord bits, and four step ...
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Table 21. µ-Law Encode-Decode Characteristics Segment #Intervals x Interval Size Number 256 128 ...
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Si3050 + Si3018/19 Table 22. A-Law Encode-Decode Characteristics Segment #Intervals x interval size Number 128 ...
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SPI Control Interface The control interface to the Si3050 is a 4-wire interface modeled on commonly available micro-controller and serial peripheral devices. The interface consists of four pins: clock (SCLK), chip select (CS), serial data input (SDI), and serial ...
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Si3050 + Si3018/19 SDO SCLK CPU CS SDI Figure 34. SPI Daisy Chain Control Architecture BRCT R SDI0 SDI1 SDI2 SDI3 ...
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SDI0-15 Figure 36. Sample SPI Control Byte for Broadcast Mode (Write Only) In Figure 35 the CID field this field is decremented in LSB to MSB order, the value decrements for each SDI down the line. ...
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Si3050 + Si3018/ CLK S DI CONTROL S DO Figure 40. Read Operation via a 16-bit SPI Port Figures 39 and 40 illustrate WRITE and READ operations via a 16-bit SPI controller. These operations require a 4-byte ...
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Within the SC channel are six Command/Indicate (C/I) bits and two handshaking bits (MR and MX). The C/I bits are used for status and command communication, whereas the handshaking ...
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Si3050 + Si3018/19 1st Byte MX Transm itter MX MR Receiver MR 1st Byte Figure 42. Monitor Handshake Timing The Idle state is achieved by the MX and MR bits being held inactive (signal is high) for two or more ...
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In this manner, multiple consecutive registers can be read or written in one transmission sequence. By correctly manipulating the MX and MR bits, a transmission sequence can continue from the beginning specified address until an invalid memory location is reached. ...
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Si3050 + Si3018/19 Idle 1st Byte Received Byte Valid New Byte Figure 43. Si3050 Monitor Receiver State Diagram ...
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MR x MXR MR x MXR Wait Idle RQT MR x RQT 1s t Byte EOM RQT nth Byte MR ack ...
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Si3050 + Si3018/19 54 Rev. 1.31 ...
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Si3050 + Si3018/19 Rev. 1.31 55 ...
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Si3050 + Si3018/19 5.40. Summary of Monitor Channel Com- mands Communication with the Si3050 should be in the following format: Byte 1: Device Address Byte Byte 2: Command Byte Byte 3: Register Address Byte Bytes 4-n: Data Bytes Bytes n+1, ...
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Receive SC Channel : MSB 7 6 CIR6 CIR5 CIR4 These bits are defined as follows: CIR6: Reserved CIR5: Reserved CIR4: ONHM CIR3: TGDE CIR2: RG CIR1: OH Data that is received must be consistent and match for at ...
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Si3050 + Si3018/19 Receive New CI Code = P? No Store in S Receive New C/I Code = Figure 47. Protocol for Receiving C/I Bits in the Si3050 5.46. Transmit SC Channel The following diagram ...
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... Line Current/Voltage Threshold Interrupt 44 Line Current/Voltage Threshold Interrupt Control 45–52 Programmable Hybrid Register 1–8 53–58 Reserved 59 Spark Quenching Control *Note: Bit is available for Si3019 line-side device only. Si3050 + Si3018/19 Table 24. Register Summary Bit 7 Bit 6 Bit 5 Bit 4 SR PWMM[1:0] INTE INTP WDTEN ...
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Si3050 + Si3018/19 Register 1. Control 1 Bit D7 D6 Name SR Type R/W Reset settings = 0000_0000 Bit Name 7 SR Software Reset Enables the DAA for normal operation Sets all registers to their reset ...
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Register 2. Control 2 Bit D7 D6 Name INTE INTP Type R/W R/W Reset settings = 0000_0011 Bit Name 7 INTE Interrupt Pin Enable The AOUT/INT pin functions as an analog output for call progress monitoring purposes. 1 ...
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... The TGD bit going active causes an interrupt on the AOUT/INT pin. 0 POLM Polarity Reversal Detect Mask (Si3019 line-side only). This interrupt is generated from bit 7 of the LVS register. When this bit transitions, it indicates that the polarity of TIP and RING is switched polarity change on TIP and RING does not cause an interrupt on the AOUT/INT pin. ...
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Register 4. Interrupt Source Bit D7 D6 Name RDTI ROVI Type R/W R/W Reset settings = 0000_0000 Bit Name 7 RDTI Ring Detect Interrupt ring signal is not occurring ring signal is detected. If ...
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... AOUT/INT pin. To clear the interrupt, write this bit POLI Polarity Reversal Detect Interrupt (Si3019 line-side only Bit 7 of the LVS register has not changed states Bit 7 of the LVS register has transitioned from from indicating the polarity of TIP and RING is switched. If the POLM bit (Register 3) and INTE bit (Register 2) are set, a hardware interrupt occurs on the AOUT/INT pin ...
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Register 5. DAA Control 1 Bit D7 D6 Name RDTN Type R Reset settings = 0000_0000 Bit Name 7 Reserved Read returns zero. 6 RDTN Ring Detect Signal Negative negative ring signal is occurring ...
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Si3050 + Si3018/19 Register 6. DAA Control 2 Bit D7 D6 Name Type Reset settings = 0001_0000 Bit Name 7:5 Reserved Read returns zero. 4 PDL Powerdown Line-Side Device Normal operation. Program the clock generator before clearing this ...
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Register 8-9. Reserved Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:0 Reserved Read returns zero. Register 10. DAA Control 3 Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:1 Reserved Read returns zero. ...
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... LSID[3:0] Line-Side ID Bits. These four bits will always read one of the following values, depending on which line-side device is used: Device Si3018 Si3019 3:0 REVA[3:0] System-Side Revision. Four-bit value indicating the revision of the Si3050 (system-side) device. Register 12. Line-Side Device Status Bit D7 D6 ...
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Register 13. Line-Side Device Revision Bit D7 D6 Name 1 Type R Reset settings = xxxx_xxxx Bit Name 7 Reserved Read returns zero. 6 Reserved This bit always reads a one. 5:2 REVB[3:0] Line-Side Device Revision. Four-bit value indicating the ...
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Si3050 + Si3018/19 Register 15. TX/RX Gain Control 1 Bit D7 D6 Name TXM Type R/W Reset settings = 0000_0000 Bit Name 7 TXM Transmit Mute Transmit signal is not muted Mutes the transmit signal. 6:4 ...
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Register 16. International Control 1 Bit D7 D6 Name OHS Type R/W Reset settings = 0000_0000 Bit Name 7 Reserved These bits may be written to a zero or one. 6 OHS On-Hook Speed. This bit, in combination with the ...
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Si3050 + Si3018/19 Register 17. International Control 2 Bit D7 D6 Name CALZ MCAL Type R/W R/W Reset settings = 0000_0000 Bit Name 7 CALZ Clear ADC Calibration Normal operation Clears the existing ADC calibration data. ...
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Bit Name 1 ROV Receive Overload. This bit is set when the receive input has an excessive input level (i.e., receive pin goes below ground). Writing this location clears this bit and the ROVI bit (Register 4, ...
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Si3050 + Si3018/19 Register 19. International Control 4 Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:3 Reserved Read returns zero. 2 OVL Receive Overload Detect. This bit has the same function as ROV (Register 17), but ...
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Register 20. Call Progress RX Attenuation Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:0 ARM[7:0] AOUT Receive Path Attenuation. When decremented from the default setting, these bits linearly attenuate the AOUT receive path signal used for ...
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Si3050 + Si3018/19 Register 22. Ring Validation Control 1 Bit D7 D6 Name RDLY[1:0] Type R/W Reset settings = 1001_0110 Bit Name Ring Delay Bits 1 and 0. 7:6 RDLY[1:0] These bits, in combination with the RDLY[2] bit (Register 23), ...
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Register 23. Ring Validation Control 2 Bit D7 D6 Name RDLY[2] Type R/W Reset settings = 0010_1101 Bit Name 7 RDLY[2] Ring Delay Bit 2. This bit, in combination with the RDLY[1:0] bits (Register 22), sets the amount of time ...
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Si3050 + Si3018/19 Register 24. Ring Validation Control 3 Bit D7 D6 Name RNGV Type R/W Reset settings = 0001_1001 Bit Name 7 RNGV Ring Validation Enable Ring validation feature is disabled Ring validation feature is ...
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Register 26. DC Termination Control Bit D7 D6 Name DCV[1:0] Type R/W Reset settings = 0000_0000 Bit Name TIP/RING Voltage Adjust. 7:6 DCV[1:0] These bits adjust the voltage on the DCT pin of the line-side device, which affects the TIP/ ...
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Si3050 + Si3018/19 Register 27. Reserved Bit D7 D6 Name Type Reset settings = xxxx_xxxx Bit Name 7:0 Reserved Do not write to these register bits. Register 28. Loop Current Status Bit D7 D6 Name Type Reset settings = 0000_0000 ...
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Register 30. AC Termination Control Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:6 Reserved Read returns zero. 5 Reserved This bit may be written to a zero or one. Enhanced Full Scale (2x) Transmit and Receive ...
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... FILT Filter Pole Selection The receive path has a low –3 dBFS corner The receive path has a low –3 dBFS corner at 200 Hz. Line Voltage Force Disable (Si3019 line-side only). 0 LVFD 0 = Normal operation The circuitry that forces the LVS register (Register 29) to all less is disabled. The LVS register may display unpredictable values at voltages between ...
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Register 32. Ground Start Control Bit D7 D6 Name Type Reset settings = 0000_0x11 Bit Name 7:3 Reserved Read returns zero. 2 TGD TIP Ground Detect The CO has grounded TIP, causing current to flow. When current ceases ...
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Si3050 + Si3018/19 Register 33. PCM/SPI Mode Select Bit D7 D6 Name PCML Type R/W R/W Reset settings = 0000_0000 Bit Name PCM Analog Loopback. 7 PCML 0 = Normal operation Enables analog data to be received from ...
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Register 34. PCM Transmit Start Count—Low Byte Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:0 TXS[7:0] PCM Transmit Start Count. PCM Transmit Start Count equals the number of PCLKs following FSYNC before data transmission begins. Register ...
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Si3050 + Si3018/19 Register 37. PCM Receive Start Count—High Byte Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:2 Reserved Read returns zero. 1:0 RXS[1:0] PCM Receive Start Count. PCM Receive Start Count equals the number of ...
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Register 39. RX Gain Control 2 Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:5 Reserved Read returns zero. 4 RGA2 Receive Gain or Attenuation Incrementing the RXG2[3:0] bits results in gaining up the ...
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Si3050 + Si3018/19 Register 40. TX Gain Control 3 Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:5 Reserved Read returns zero. 4 TGA3 Transmit Gain or Attenuation Incrementing the TGA3[3:0] bits results in ...
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Register 41. RX Gain Control 3 Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:5 Reserved Read returns zero. 4 RGA3 Receive Gain or Attenuation Incrementing the RXG3[3:0] bits results in gaining up the ...
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Si3050 + Si3018/19 Register 42. GCI Control Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:4 Reserved Read returns zero. 3:2 GCIF[1:0] GCI Data Format A-Law µ-Law 8-bit linear. The top ...
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... These bits determine the threshold at which an interrupt is generated from either the LCS or LVS register. This interrupt can be generated to occur when the line current or line voltage rises above or drops below the value in the CVT[7:0] register. Register 44. Line Current/Voltage Threshold Interrupt Control (Si3019 line-side only) Bit D7 ...
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Si3050 + Si3018/19 Register 45. Programmable Hybrid Register 1 Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:0 HYB1[7:0] Programmable Hybrid Register 1. These bits can be programmed with a coefficient value to adjust the hybrid response ...
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Register 47. Programmable Hybrid Register 3 Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:0 HYB3[7:0] Programmable Hybrid Register 3. These bits can be programmed with a coefficient value to adjust the hybrid response to reduce near-end ...
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Si3050 + Si3018/19 Register 49. Programmable Hybrid Register 5 Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:0 HYB5[7:0] Programmable Hybrid Register 5. These bits can be programmed with a coefficient value to adjust the hybrid response ...
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Register 51. Programmable Hybrid Register 7 Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:0 HYB7[7:0] Programmable Hybrid Register 7. These bits can be programmed with a coefficient value to adjust the hybrid response to reduce near-end ...
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Si3050 + Si3018/19 Register 59. Spark Quenching Control Bit D7 D6 Name SQ1 Type R/W Reset settings = xxxx_xxxx Bit Name 7 Reserved Always write this bit to zero. Spark Quenching. 6 SQ1 This bit, in combination with the OHS ...
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... A —UL1950 3 PPENDIX RD Introduction Although designs using the Si3018 and Si3019 comply with UL1950 3rd Edition and pass all overcurrent and overvoltage tests, there are still several issues to consider. Figure 48 shows two designs that can pass the UL1950 overvoltage tests and electromagnetic emissions. The ...
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Si3050 + Si3018/19 7. Pin Descriptions: Si3050 AOUT/INT Pin # Pin Name 1 SDO Serial Port Data Output. Serial port control data output. 2 SDI Serial Port Data Input. Serial port control data input Chip Select Input. An ...
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Table 25. Si3050 Pin Descriptions (Continued) Pin # Pin Name 11 TGD TIP Ground Detect Input. Used to detect current flowing in TIP for supporting ground start applications. 12 TGDE TIP Ground Detect Enable Output. Control signal for the ground ...
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Si3050 + Si3018/19 8. Pin Descriptions: Si3018/19 Pin # Pin Name 1 QE Transistor Emitter. Connects to the emitter of Q3. 2 DCT DC Termination. Provides dc termination to the telephone network Receive Input. Serves as the receive ...
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Pin # Pin Name 14 DCT3 DC Termination 3. Provides dc termination to the telephone network. 15 IGND Isolated Ground. Connects to ground on the line-side interface. 16 DCT2 DC Termination 2. Provides dc termination to the telephone network. Si3050 ...
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... System-side Chipset Region (TSSOP) Si3050 + Enhanced Global Si3050-E-FT Si3019-F-FS Si3019-F-FT Si3019 Si3050 + Enhanced Global Si3050-E-GT Si3019-F-GS Si3019-F-GT Si3019 Si3050 + Global Si3050-E-FT Si3018-F-FS Si3018-F-FT Si3018 Note: Refer to "10. Product Identification" on page 102 for more information on part naming conventions. 10. Product Identification The product identification number is a finished goods part number or is specified by a finished goods part number, such as a special customer part number ...
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Package Outline: 20-Pin TSSOP Figure 49 illustrates the package details for the Si3050. Table 26 lists the values for the dimensions shown in the illustration. Figure 49. 20-Pin Thin Shrink Small Outline Package (TSSOP) Si3050 + Si3018/19 Rev. 1.31 ...
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Si3050 + Si3018/19 Table 26. 20-Pin TSSOP Package Diagram Dimensions Dimension θ aaa bbb ccc Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning ...
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Package Outline: 16-Pin SOIC Figure 50 illustrates the package details for the Si3018/19. Table 27 lists the values for the dimensions shown in the illustration. Figure 50. 16-Pin Small Outline Integrated Circuit (SOIC) Package Si3050 + Si3018/19 Rev. 1.31 ...
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Si3050 + Si3018/19 Table 27. 16-Pin SOIC Package Diagram Dimensions Dimension θ aaa bbb ccc ddd Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. ...
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Package Outline: 16-Pin TSSOP Figure 51 illustrates the package details for the Si3018/19. Table 28 lists the values for the dimensions shown in the illustration. Figure 51. 16-Pin Thin Shrink Small Outline Package (TSSOP) Si3050 + Si3018/19 Rev. 1.31 ...
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Si3050 + Si3018/19 Table 28. 16-Pin TSSOP Package Diagram Dimensions Dimension θ aaa bbb ccc Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning ...
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S L Si3050 S ILICON ABS AN16: Multiple Device Support AN17: Designing for International Safety Compliance AN30: Ground Start Implementation with Silicon Laboratories’ DAAs AN67: Layout Guidelines AN72: Ring Detection/Validation with the Si305x DAAs AN77: ...
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Si3050 + Si3018/ OCUMENT HANGE IST Revision 1.01 to Revision 1.1 Added package thermal information in Table 1, “Recommended Operating Conditions and Thermal Information,” on page 5. Added Note 10 to the transhybrid balance parameter ...
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N : OTES Si3050 + Si3018/19 Rev. 1.31 111 ...
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... Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized ap- plication, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages. Silicon Laboratories and Silicon Labs are trademarks of Silicon Laboratories Inc. Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders. ...