SI3019-KT Silicon Laboratories Inc, SI3019-KT Datasheet
SI3019-KT
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SI3019-KT Summary of contents
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Features Complete DAA includes the following: Programmable line interface AC termination DC termination Ring detect threshold Ringer impedance 80 ...
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Si3018/19/10 2 Rev. 1.03 ...
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... Upgrading from the Si3034/35/44 to Si3056 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.2. Line-Side Device Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.3. Power Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.4. Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 5.5. Isolation Barrier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.6. Transmit/Receive Full Scale Level (Si3019 Line-Side Only 5.7. Parallel Handset Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.8. Line Voltage/Loop Current Sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.9. Off-Hook . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5.10. Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.11. DC Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5 ...
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Si3018/19/10 9. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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... The Si3056 specifications are guaranteed when the typical application circuit (including component tolerance) and the Si3056 and any Si3018 or Si3019 are used. See Figure 17 on page 18 for typical application schematic. 2. All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions. ...
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Si3018/19/10 Table 2. Loop Characteristics = = (V 3 °C for K-Grade Parameter Symbol DC Termination Voltage V DC Termination Voltage V DC Termination Voltage V DC Termination Voltage V DC ...
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Table 3. DC Characteristics 3 ° Parameter High Level Input Voltage Low Level Input Voltage High Level Output Voltage Low Level Output Voltage Input Leakage Current 1 ...
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... When using the Si3010 line-side, the typical THD values will be approximately 10 dB higher. 10 log (RMS V /RMS V CID CID application circuit in Figure 17. With the enhanced CID circuit, the V increases to 62 dB. 11. Available on the Si3019 line-side device only. 8 Symbol Test Condition /5120 PLL2 ...
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... When using the Si3010 line-side, the typical THD values will be approximately 10 dB higher. 10 log (RMS V /RMS V CID CID application circuit in Figure 17. With the enhanced CID circuit, the V increases to 62 dB. 11. Available on the Si3019 line-side device only. Symbol Test Condition THD ILIM = 0, DCV = 00, DCR = mA, MINI = 11 L ...
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Si3018/19/10 Table 5. Absolute Maximum Ratings Parameter DC Supply Voltage Input Current, Si3056 Digital Input Pins Digital Input Voltage Operating Temperature Range Storage Temperature Range Note: Permanent device damage can occur if the above absolute maximum ratings are exceeded. Restrict ...
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Table 7. Switching Characteristics—Serial Interface (Master Mode, DCE = 3 °C for K-Grade Parameter Cycle time, SCLK SCLK Duty Cycle Delay Time, SCLK↑ to FSYNC↓ Delay Time, SCLK↑ ...
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Si3018/19/10 Table 8. Switching Characteristics—Serial Interface (Master Mode, DCE = 1, FSD = Charge Pump 3 1,2 Parameter Cycle Time, SCLK SCLK Duty Cycle Delay Time, SCLK ↑ to ...
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Table 9. Switching Characteristics—Serial Interface (Master Mode, DCE = 1, FSD = 3 °C for K-Grade Parameter Cycle Time, SCLK SCLK Duty Cycle Delay Time, SCLK ...
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Si3018/19/10 Table 10. Switching Characteristics—Serial Interface (Slave Mode, DCE = 1, FSD = Charge Pump 3 Parameter Cycle Time, MCLK Setup Time, FSYNC ↑ before MCLK ↓ * Delay ...
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Table 11. Digital FIR Filter Characteristics—Transmit and Receive (V = 3.0 to 3.6 V, Sample Rate = 8 kHz Parameter Passband (0.1 dB) Passband (3 dB) Passband Ripple Peak-to-Peak Stopband Stopband Attenuation Group Delay Note: Typical FIR filter ...
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Si3018/19/10 Figure 7. FIR Receive Filter Response Figure 8. FIR Receive Filter Passband Ripple For Figures 7–10, all filter plots apply to a sample rate kHz. 16 Figure 9. FIR Transmit Filter Response Figure 10. FIR ...
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Figure 11. IIR Receive Filter Response Figure 12. IIR Receive Filter Passband Ripple Figure 13. IIR Transmit Filter Response Si3018/19/10 Figure 14. IIR Transmit Filter Passband Ripple Figure 15. IIR Receive Group Delay Figure 16. IIR Transmit Group Delay Rev. ...
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Si3018/19/10 2. Typical Application Schematic 18 Rev. 1.03 ...
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Bill of Materials Component(s) C1 C5, C6, C50, C51 C7 C8, C9 C10 3 C30, C31 Not installed, 120 pF, 250V, X7R, ±10% 2 D1, D2 Dual Diode, 225 mA, 300 V, CMPD2004S FB1, FB2 ...
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Si3018/19/10 4. AOUT PWM Output Figure 18 illustrates an optional circuit to support the pulse width modulation (PWM) output capability of the Si3056 for call progress monitoring purposes. Set the PWME bit (Register 1, bit 3) to enable this mode. ...
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... Globally-compliant, enhanced features line-side ® customers device—Targets embedded and voice applications with global DAA requirements. Use the Si3019 line- side device for this configuration. The Si3019 contains all the features available on the Si3018, plus the following additional features/enhancements: Sixteen selectable ac terminations to increase return loss and trans-hybrid loss performance ...
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... Yes (HW interrupt) Yes (HW interrupt) Yes (HW interrupt Yes Yes Yes (MCLK active) Yes (MCLK active) Yes (MCLK active interrupts Yes Yes No Yes +3.2 dBm 0 dBm Rev. 1.03 Si3056 Si3018 Si3019 Yes Yes SSI SSI 3 kbps 56 kbps 16-bit 16-bit 8-bit 8-bit 16 kHz 16 kHz steps 0 ...
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... Latvia 0 1 Lebanon 0 1 Note: 1. Supported for loop current ≥ 20 mA. 2. Available with Si3019 line-side only. 3. Available with Si3018 line-side only. 4. See "5.11.DC Termination" on page 27 for DCV and MINI settings. 5. ACIM is 0000 for data applications and 1010 for voice applications ...
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... USA 0 0 Yemen 0 0 Note: 1. Supported for loop current ≥ 20 mA. 2. Available with Si3019 line-side only. 3. Available with Si3018 line-side only. 4. See "5.11.DC Termination" on page 27 for DCV and MINI settings. 5. ACIM is 0000 for data applications and 1010 for voice applications ...
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... DCT pin voltage with the DVC[1:0] bits. 5.8. Line Voltage/Loop Current Sensing The Si3056 can measure loop current and line voltage with the Si3010, Si3018, and the Si3019 line-side devices. The 8-bit LCS2[7:0] and LCS[4:0] registers report loop current. The 8-bit LVS[7:0] register reports line voltage ...
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Si3018/19/10 These registers can help determine the following: When on-hook, detect if a line is connected. When on-hook, detect if a parallel phone is off-hook. When off-hook, detect if a parallel phone goes on or off-hook. Detect if enough loop ...
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... Only the magnitude of the measured value is used to compare to the threshold programmed into the CVT[7:0] bits, and thus only positive numbers should be used as a threshold. This line current/voltage threshold interrupt is only available with the Si3019 line-side device. 5.11. DC Termination The DAA has programmable settings for dc impedance, minimum operational loop current, and TIP/RING voltage ...
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... AC Termination The Si3056 has four ac termination impedances with the Si3018 line-side device and sixteen ac termination impedances with the Si3019 line-side device. The ACT and ACT2 bits select the ac impedance on the Si3018 line-side device. The ACIM[3:0] bits select the ac impedance on the Si3019. The available ac termination settings are listed for the line-side devices in Tables 17 and 18 ...
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There are two selections that are useful for satisfying non-standard ac termination requirements. The 350 Ω + (1000 Ω || 210 nF) impedance selection is the ANSI/ EIA/TIA 464 compromise impedance network for trunks. The last ac termination selection, ACIM[3:0] ...
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Si3018/19/10 When RFWE is 1, DTX sits at approximately +1228 while the RNG1-RNG2 voltage is between the thresholds. When the ring becomes positive, DTX transitions to +32767. When the ring signal goes near 0, DTX remains near 1228. As the ...
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Pulse Dialing and Spark Quenching Pulse dialing results from going off- and on-hook to generate make and break pulses. The nominal rate is 10 pulses per second. Some countries have strict specifications for pulse fidelity that include make and ...
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Si3018/19/ TIP From Line C3 RING Figure 22. Billing Tone Filter L1 must carry the entire loop current. The series resistance of the inductors is important to achieve a narrow and deep notch. This design has more ...
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The host processor must detect the presence of this tone. 2. The DAA must then check for another parallel device on the same line. This is accomplished by briefly going on-hook, measuring the line voltage, and then returning ...
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Si3018/19/10 O ff-Hook Counter LIN E and C alibration O n-H ook (402. nom inally [ [ ...
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... ATX[2:0] bits. The transmit path also can be muted with the TXM bit (Register 15). When using the Si3019 line-side device, the Si3056 provides even more flexible gain and attenuation settings. The TXG2 and RXG2 bits (registers 38–39) enable gain or attenuation increments for the transmit and receive paths ...
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... IIR and FIR filters. The IIR filter provides a shorter, but non-linear, group delay alternative to the default FIR filter and only operates with an 8 kHz sample rate. Also, on the Si3019 line-side device, the FILT bit (Register 31, bit 1) selects a –3 dB low frequency pole when cleared and 200 Hz when set ...
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PLL Lock Times The Si3056 changes sample rates quickly. However, lock time varies based on the programming of the clock generator. The following relationships describe the boundaries on PLL locking time: PLL1 lock time < PLL2 lock ...
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Si3018/19/10 provides software control of the secondary frames alternative method, the FC pin can serve as a hardware flag for requesting a secondary frame. The external DSP can turn on the 16-bit TX mode by setting the SB ...
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SRC[3:0] bits (Register 7, bits programmed with the proper sample rate value before the sampled line data is valid. The SCLK pin of the slave connect in this configuration. The delay between FSYNC input and delayed frame ...
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Si3018/19/10 passes through the internal filters and transmitted on SDO which introduces approximately attenuation on the SDI signal received. The group delay of both transmit and receive filters exists between SDI and SDO. Clearing the PDL bit disables this mode ...
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... Prim ary FC 0 D15 – (Software FC Bit) SDI XMT Data SDO RCV Data 16 SCLKS 128 SCLKS Figure 27. Software FC/RGDT Secondary Request Table 22. Revision Values Si3056 Si3018 Si3019 0001 0001 0001 0010 0010 0010 0011 0011 0011 0100 0100 0100 0101 0101 ...
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Si3018/19/10 Com m unications Fram e 1 (CF1) FSYNC Prim ary FC 0 D15–D0 SDI XMT Data SDO RCV Data 16 SCLKS 128 SCLKS Figure 28. Hardware FC/RGDT Secondary Request FSYNC (mode 0) FSYNC (mode 1) SDI SDO Figure 29. ...
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FSYNC (mode 0) FSYNC (mode 1) SDI R/W SDO Figure 30. Secondary Communication Data Format—Write Cycle Master Serial Mode 1 Reg 14: NSLV = 1, SSEL = 2, FSD = 0, DCE = 1 Slave 1 Serial Mode 2 Reg ...
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Si3018/19/10 Master Serial Mode 1 Reg 14: NSLV = 1, SSEL = 2, FSD = 1, DCE = 1 Slave 1 Serial Mode 2 Reg 14 Reset values: NSLV = 1, SSEL = 3, FSD = 1, DCE = 1 ...
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Si3018/19/10 Rev. 1.03 45 ...
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Si3018/19/10 M aster Serial M ode 0 Reg 14: NSLV = 1, SSEL = 2, FSD = 0, DCE = 1 Slave 1 Serial M ode 2 Reg 14 Reset values: NSLV = 1, SSEL = 3, FSD = 1, ...
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Host SCLK SDO SDI FSYNC INTO 47 kΩ 47 kΩ VCC 47 kΩ Figure 36. Typical Connection for Multiple DAAS Rev. 1.03 Si3018/19/10 MCLK Si3056—Master MCLK SCLK SDI SDO FSYNC FC/RGDT RGDT/FSD/M1 VCC M0 47 kΩ Si3056—Slave 1 MCLK NC ...
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... Line Current/Voltage Threshold Interrupt Control 45–52 Programmable Hybrid Register 1–8 53–58 Reserved 59 Spark Quenching Control Notes: 1. Bit is available for Si3019 line-side device only. 2. Bit is available for Si3010 and Si3018 line-side device only. 48 Table 23. Register Summary Bit 7 Bit 6 Bit 5 Bit 4 SR PWMM[1:0] ...
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Register 1. Control 1 Bit Name SR PWMM[1:0] Type R/W Reset settings = 0000_0000 Bit Name 7 SR Software Reset Enables the DAA for normal operation Sets all registers to their reset value. ...
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Si3018/19/10 Register 2. Control 2 Bit Name INTE INTP Type R/W R/W Reset settings = 0000_0011 Bit Name 7 INTE Interrupt Pin Enable The AOUT/INT pin functions as an analog output for call progress monitoring ...
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Register 3. Interrupt Mask Bit Name RDTM ROVM FDTM Type R/W R/W R/W Reset settings = 0000_0000 Bit Name 7 RDTM Ring Detect Mask ring signal does not cause an interrupt on the AOUT/INT ...
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Si3018/19/10 Register 4. Interrupt Source Bit Name RDTI ROVI FDTI Type R/W R/W R/W Reset settings = 0000_0000 Bit Name 7 RDTI Ring Detect Interrupt ring signal is not occurring ring ...
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Bit Name 1 DLCSI Delta Loop Current Sense Interrupt 0 = The LCS bits have not changed value The LCS bits have changed value; a hardware interrupt occurs on the AOUT/INT pin. This bit must be written to ...
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Si3018/19/10 Register 6. DAA Control 2 Bit Name Type Reset settings = 0001_0000 Bit Name 7:5 Reserved Read returns zero. 4 PDL Powerdown Line-Side Device Normal operation. Program the clock generator before clearing this bit. ...
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Register 8. PLL Divide N Bit Name Type Reset settings = 0000_0000 (serial mode 0, 1) Reset settings = 0001_0011 (serial mode 2) Bit Name 7:0 N[7:0] PLL N Divider. Contains the (value –1) for determining the ...
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... Bit Name 7:4 LSID[3:0] Line-Side ID Bits. These four bits will always read one of the following values depending on which line-side device is used. Si3018 Si3019 Si3010 3:0 REVA[3:0] System-Side Revision. Four-bit value indicating the revision of the system-side device. Register 12. Line-Side Device Status Bit D7 ...
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Register 13. Line-Side Device Revision Bit Name 0 Type Reset settings = xxxx_xxxx Bit Name 7 Reserved Read returns zero This bit always reads a zero. 5:2 REVB[3:0] Line-Side Device Revision. Four-bit value indicating the ...
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Si3018/19/10 Register 14. Serial Interface Control Bit Name NSLV[2:0] Type R/W Reset settings = 0000_0000 (serial mode 0,1) Reset settings = 0011_1101 (serial mode 2) Bit Name 7:5 NSLV[2:0] Number of Slaves devices. 000 = 0 slaves. ...
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... Analog Receive Gain. 000 = 0 dB gain 001 = 3 dB gain 010 = 6 dB gain 011 = 9 dB gain 1xx = 12 dB gain Note: Write these bits to zero when using the finer resolution transmit and receive gain/attenuation registers 38–41 available only with the Si3019 line-side device RXM ARX[2:0] ...
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Si3018/19/10 Register 16. International Control 1 Bit Name ACT2 OHS ACT Type RW R/W R/W Reset settings = 0000_0000 Bit Name 7 ACT2 AC Termination Select 2 (Si3018 line-side device only). Works with the ACT bit to ...
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Register 17. International Control 2 Bit Name CALZ MCAL CALD Type R/W R/W R/W Reset settings = 0000_0000 Bit Name 7 CALZ Clear ADC Calibration Normal operation Clears the existing calibration data. This ...
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Si3018/19/10 Register 18. International Control 3 Bit Name Type Reset settings = 0000_0000 Bit Name 7:2 Reserved Read returns zero or one. 1 RFWE Ring Detector Full-Wave Rectifier Enable. When RNGV (Register 24) is disabled, this bit ...
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Register 19. International Control 4 Bit Name Type Reset settings = 0000_0000 Bit Name 7:3 Reserved Read returns zero. 2 OVL Receive Overload Detect. This bit has the same function as ROV in Register 17, but clears ...
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Si3018/19/10 Register 20. Call Progress Receive Attenuation Bit Name Type Reset settings = 0000_0000 Bit Name 7:0 ARM[7:0] AOUT Receive Path Attenuation. When decremented from the default setting, these bits linearly attenuate the AOUT receive path signal ...
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Register 22. Ring Validation Control 1 Bit Name RDLY[1:0] Type R/W Reset settings = 1001_0110 Bit Name 7:6 RDLY[1:0] Ring Delay Bits 1 and 0. These bits, in combination with the RDLY[2] bit (Register 23), set the ...
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Si3018/19/10 Register 23. Ring Validation Control 2 Bit Name RDLY[2] RTO[3:0] Type R/W Reset settings = 0010_1101 Bit Name 7 RDLY[2] Ring Delay Bit 2. This bit, in combination with the RDLY[1:0] bits (Register 22), set the ...
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Register 24. Ring Validation Control 3 Bit Name RNGV Type R/W R Reset settings = 0001_1001 Bit Name 7 RNGV Ring Validation Enable Ring validation feature is disabled Ring validation feature is enabled ...
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Si3018/19/10 Register 25. Resistor Calibration Bit Name RCALS RCALM RCALD Type R R/W R/W Reset settings = xx0x_xxxx Bit Name 7 RCALS Resistor Auto Calibration Resistor calibration is not in progress Resistor calibration ...
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Register 26. DC Termination Control Bit Name DCV[1:0] MINI[1:0] Type R/W Reset settings = 0000_0000 Bit Name 7:6 DCV[1:0] TIP/RING Voltage Adjust. Adjust the voltage on the DCT pin of the line-side device, which affects the TIP/RING ...
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Si3018/19/10 Register 27. Reserved Bit Name Type Reset settings = xxxx_xxxx Bit Name 7:0 Reserved Do not read or write. Register 28. Loop Current Status Bit Name Type Reset settings = 0000_0000 Bit Name ...
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... Register 30. AC Termination Control (Si3019 line-side device only) Bit Name Type Reset settings = 0000_0000 Bit Name 7:5 Reserved Read returns zero. 4 FULL2 Enhanced Full Scale (2X) Transmit and Receive Mode (line-side Revision E or later Default 1 = Transmit/Receive 2X Full Scale This bit changes the full scale of the ADC and DAC from 0 min to +6 dBm into 600 Ω load (or 1 ...
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... Bit Name 7 FULL Full Scale Transmit and Receive Mode (Si3019 line-side device only Default Transmit/receive full scale. This bit changes the full scale of the ADC and DAC from 0 min to +3.2 dBm into a 600 Ω load (or 1 dBV into all reference impedances). When this bit is set, the DCV[1:0] bits (Register 26) should be set to all 1s to avoid distortion at low loop currents ...
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... Register 32-37. Reserved Bit Name Type Reset settings = 0000_0000 Bit Name 7:0 Reserved Read returns zero. Register 38. TX Gain Control 2 (Si3019 Line-Side Device Only) Bit Name Type Reset settings = 0000_0000 Bit Name 7:5 Reserved Read returns zero. 4 TGA2 Transmit Gain or Attenuation 2. ...
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... Si3018/19/10 Register 39. RX Gain Control 2 (Si3019 Line-Side Device Only) Bit Name Type Reset settings = 0000_0000 Bit Name 7:5 Reserved Read returns zero. 4 RGA2 Receive Gain or Attenuation Incrementing the RXG2[3:0] bits results in gaining up the receive path Incrementing the RXG2[3:0] bits results in attenuating the receive path. ...
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... Register 40. TX Gain Control 3 (Si3019 Line-Side Device Only) Bit Name Type Reset settings = 0000_0000 Bit Name 7:5 Reserved Read returns zero. 4 TGA3 Transmit Gain or Attenuation Incrementing the TXG3[3:0] bits results in gaining up the transmit path Incrementing the TXG3[3:0] bits results in attenuating the transmit path. ...
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... Si3018/19/10 Register 41. RX Gain Control 3 (Si3019 Line-Side Device Only) Bit Name Type Reset settings = 0000_0000 Bit Name 7:5 Reserved Read returns zero. 4 RGA3 Receive Gain or Attenuation Incrementing the RXG3[3:0] bits results in gaining up the receive path Incrementing the RXG3[3:0] bits results in attenuating the receive path. ...
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... Determines the threshold at which an interrupt is generated from either the LCS or LVS regis- ter. Generate this interrupt to occur when the line current or line voltage rises above or drops below the value in the CVT[7:0] register. Register 44. Line Current/Voltage Threshold Interrupt Control (Si3019 Line-Side Device Only) Bit D7 ...
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Si3018/19/10 Register 45. Programmable Hybrid Register 1 Bit Name Type Reset settings = 0000_0000 Bit Name 7:0 HYB1[7:0] Programmable Hybrid Register 1. These bits are programmed with a coefficient value to adjust the hybrid response to reduce ...
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Register 47. Programmable Hybrid Register 3 Bit Name Type Reset settings = 0000_0000 Bit Name 7:0 HYB3[7:0] Programmable Hybrid Register 3. These bits are programmed with a coefficient value to adjust the hybrid response to reduce near-end ...
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Si3018/19/10 Register 49. Programmable Hybrid Register 5 Bit Name Type Reset settings = 0000_0000 Bit Name 7:0 HYB5[7:0] Programmable Hybrid Register 5. These bits are programmed with a coefficient value to adjust the hybrid response to reduce ...
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Register 51. Programmable Hybrid Register 7 Bit Name Type Reset settings = 0000_0000 Bit Name 7:0 HYB7[7:0] Programmable Hybrid Register 7. These bits are programmed with a coefficient value to adjust the hybrid response to reduce near-end ...
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Si3018/19/10 Register 59. Spark Quenching Control Bit Name SQ1 Type R/W Reset settings = xxxx_xxxx Bit Name 7 Reserved Always write this bit to zero. Spark Quenching. 6 SQ1 This bit, in combination with the OHS bit ...
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A —UL1950 3 PPENDIX RD Although designs using the Si3056 comply with the UL1950 3rd edition and pass all overcurrent and overvoltage tests, there are still several issues to consider. Figure 37 shows two designs that can pass the UL1950 ...
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Si3018/19/10 7. Pin Descriptions: Si3056 Pin # Pin Name 1 MCLK Master Clock Input. High speed master clock input. Generally supplied by the system crystal clock or modem/DSP. 2 FSYNC Frame Sync Output. Data framing signal that indicates the start ...
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Table 24. Si3056 Pin Descriptions (Continued) Pin # Pin Name 11 AOUT/INT Analog Speaker Out/Interrupt. Provides an analog output signal for driving a call progress speaker or a hardware interrupt for multiple sources of interrupts. 12 GND Ground. Connects to ...
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Si3018/19/10 8. Pin Descriptions: Si3018/19/10 Table 25. Si3018/19/10 Pin Descriptions Pin # Pin Name 1 QE Transistor Emitter. Connects to the emitter of Q3. 2 DCT DC Termination. Provides dc termination to the telephone network Receive Input. Serves ...
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Table 25. Si3018/19/10 Pin Descriptions (Continued) Pin # Pin Name 13 QB Transistor Base. Connects to the base of transistor Q4. 14 DCT3 DC Termination 3. Provides dc termination to the telephone network. 15 IGND Isolated Ground. Connects to ground ...
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... Si3019-KS Si3056-KS Si3010-KS Si3019-X-FS GCI Si3018-X-FS GCI Si3018-X-FS Si3056-FS Si3019-X-FS or Si3056-C-FS Si3010-X-FS Rev. 1.03 Digital Line Temperature (TSSOP) (TSSOP) Si3050-KT Si3019- °C Si3050-KT Si3018- °C Si3018- °C Si3019- ° °C Si3019-X- °C Si3050-FT or Si3018-X- °C Si3050-X-FT Si3018-X- °C Si3019-X- ° °C ...
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... Evaluation Board Ordering Guide Part Number Line-Side Device Si3056PPT-EVB Si3018 Parallel Port Si3056PPT1-EVB Si3019 Parallel Port Si3056PPT2-EVB Si3010 Parallel Port Si3056SSI-EVB Si3018 Serial Interface with Buffer Direct Connection to processor Si3056SSI1-EVB Si3019 Serial Interface with Buffer Si3056SSI2-EVB Si3010 Serial Interface with Buffer ...
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Si3018/19/10 11. Product Selection and Identification Guide Device Finished Goods Part Number Si3056 Si3056-X-KS Commercial part Si3056 Si3056-X-FS Commercial part, lead-free version Si3056 Si3056-X-XS4 Customer-specific bond option Si3056 Si3056-X-ZS4 Customer-specific bond option, lead-free version Si3056 Si3056-X-XS5 Customer-specific bond option Si3056 ...
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Package Outline: 16-Pin SOIC Figure 38 illustrates the package details for the Si3056/18/19/10. Table 26 lists the values for the dimensions shown in the illustration aaa - Seating Plane ...
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... Updated “5.8.1.Line Voltage Measurement” functional description. Updated “5.10.Interrupts” functional description. Updated “5.11.DC Termination” functional description. Updated “6.Control Registers” to reflect LVFD bit available exclusively with the Si3019 line-side. 92 Updated the following bit descriptions: R4.7 R12.4–0 R14.2 R17.4 ...
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... Updated Table 24, “Si3056 Pin Descriptions,” on page 84. Updated Figure 19 on page 26. Updated "5.6.Transmit/Receive Full Scale Level (Si3019 Line-Side Only)" on page 25 of Functional description to include new enhanced full scale mode. The following bits have been added, but will only be supported with Si3018/19/10 Revision E or later line- side devices ...
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Si3018/19/ ILICON ABORATORIES Application Note 13: Silicon DAA Software Guidelines Application Note 16: Multiple Device Support Application Note 17: Designing for International Safety Compliance Application Note 67: Layout Guidelines Application Note 72: Ring Detection/Validation with the Si305x DAAs ...
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N : OTES Si3018/19/10 Rev. 1.03 95 ...
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... Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized ap- plication, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages. Silicon Laboratories and Silicon Labs are trademarks of Silicon Laboratories Inc. Other products or brand names mentioned herein are trademarks or registered trademarks of their respective holders. ...