MCP795W10-I/SL Microchip Technology, MCP795W10-I/SL Datasheet - Page 17

• Manufacturer Part Number: MCP795W10-I/SL
• Description: SPI GPP RTCC, 1Kb EE, 64B SRAM, WD Timer, Event Detect, ID 14 SOIC .150in TUBE
• Manufacturer: Microchip Technology

REGISTER 5-12:
 2011-2012 Microchip Technology Inc.
bit 7
Legend:
R = Readable bit
bit 7
bit 6
bit 5:4
bit 3
bit 2
bit 1-0
Note 1:
EVHIF
R/W
Please see
bit 6
EVHIF: High-Speed Event Interrupt Flag bit
When the configured number of high-speed events has occurred, the IRQ pin is asserted and the
EVHIF bit is set in hardware. To clear the interrupt and the IRQ pin the EVHIF bit must be cleared in
software.
EVLIF: Low-Speed Event Interrupt Flag bit
When an event occurs on the low-speed pin, this IRQ pin is asserted and the EVLIF bit is set. This bit
must be cleared by software to reset the module and clear the IRQ pin.
EVEN<1:0>: Event Detect Configuration bits
These two bits determine what combination of the high and low-speed modules are enabled.
EVWDT: EVHS Watchdog Timer Reset Enable bit
Setting this bit overrides any setting for the High-Speed Event Detection and allows the EVHS pin to
clear the Watchdog Timer. This is edge triggered. Either an H-L or L-H transition will clear the WDT.
EVLDB: Low-Speed Event Detect Debounce Configuration bit
This is the Low-Speed Event Debounce setting. Depending on the state of this bit, the low-speed pin
will have to remain at the same state for the following periods to be considered valid.
EVHS<1:0>: High-Speed Event Detect Configuration bits
Determines how many high-speed events must occur before the EVHIF bit is set.
All of these events must occur within 250 ms (based on the uncalibrated 32.768 kHz clock).
- 00 – Both modules are Off
- 01 – Low-speed module enabled, high speed disabled
- 10 – Low-speed module disabled, high speed enabled
- 11 – Both modules are enabled
- 0 – 31.25 ms
- 1 – 500 ms
- 00 – 1
- 01 – 4
- 10 – 16
- 11 – 32
EVLIF
R/W
EVENT DETECT 0
Section 9.1.4, Event Detection
st
th
th
nd
Event
Event
bit 5
W = Writable bit
Event
Event
EVEN1
R/W
X
0B
bit 4
EVEN0
MCP795WXX/MCP795BXX
R/W
Preliminary
for more information.
bit 3
U = Unimplemented bit, read as ‘0’
EVWDT
R/W
EVLDB
R/W
bit 2
EVHS1
R/W
bit 1
DS22280B-page 17
bit 0
EVHS0
R/W