MCP795W10-I/SL Microchip Technology, MCP795W10-I/SL Datasheet - Page 30

• Manufacturer Part Number: MCP795W10-I/SL
• Description: SPI GPP RTCC, 1Kb EE, 64B SRAM, WD Timer, Event Detect, ID 14 SOIC .150in TUBE
• Manufacturer: Microchip Technology

MCP795WXX/MCP795BXX
9.1.2
The MCP795W20 features a push-pull pin CLKOUT
that can supply a digital signal based on a division of
the main 32.768 kHz clock. If this function is not used
the pin may be directly controlled using the OUT bit in
the Control register (0x08). In V
logic low. In V
stated. For the MCP795BXX devices, this pin functions
as a Power-up Boot clock. A 32.768 kHz clock is
enabled upon application of V
9.1.3
The on-board Watchdog Timer is configured by loading
the register at address 0x0A. The WDT is not available
when the MCP795XXX is operating from the V
ply. When in this condition, the WDT is disabled by the
hardware and must be re-enabled when V
restored. The output of the WDT is based on the un-
calibrated 32.768 kHz oscillator.
Description of WDT Bits:
• Bit 7 is a read/write bit that is set and cleared by
• Bit 6 is a read/write bit that is set in hardware
• Bit 5 is a read/write bit and is set to enable a 64-
• Bit 4 is a read/write bit that is used to select the
• Bits <3:0> are read/write bits that are used to set
DS22280B-page 30
software. This bit is set to enable the WDT func-
tion and cleared to disable the function. A V
power fail will cause this bit to be cleared and not
re-enabled when V
when the WDT times out and the WDO pin is
asserted. This bit must be cleared in software to
restart the WDT.
second delay before the WDT starts to count. If
this bit is set and the WDTIF bit is cleared then
there will be a 64-second delay before the WDT
starts to count. This bit should be set before the
WDTEN bit is set.
pulse width on the WDO pin when the WDT times
out.
- 0 – 122 us Pulse
- 1 – 125 ms Pulse
the WDT time-out period as below (all times are
based off the uncalibrated crystal reference). Bit 3
should be cleared and is reserved for future use:
- 000 – 977 us
- 001– 15.6 ms
- 010 – 62.5 ms
- 011 – 125 ms
- 100 – 1s
- 101 – 16s
- 110 – 32s
- 111 – 64s
CLOCKOUT FUNCTION
WATCHDOG TIMER
DD
POR condition, the CLKOUT is tri-
CC
is restored.
CC
BAT
.
mode, CLKOUT is
BAT
CC
CC
sup-
Preliminary
is
To reset the WDT the CLRWDT instruction must be
issued over the SPI interface, as shown in
If the WDT is not cleared with the CLRWDT command
before time-out then the WDO pin will assert and the
WDTIF bit will be set. The WDTIF bit must be cleared
by software to restart the WDT.
9.1.4
The on-chip event detection consists of two separate
detection circuits.
The high-speed circuit is designed to operate with a
digital signal from the output of an external signal con-
ditioning circuit. The input is edge triggered, and will
generate an interrupt when the correct number of
events has occurred.
The low-speed circuit is designed to operate directly
with mechanical switches and support built-in switch
debounce.
Registers associated with the event detection module:
• EVHIF – When the configured number of high
• EVLIF – When an event occurs on the low-speed
• EVEN<1:0> – These two bits determine what
• EVWDT – setting this bit overrides any setting for
• EVLDB – This is the low-speed event debounce
speed events has occurred the IRQ pin is
asserted and the EVHIF bit is set. This bit must be
cleared by software to reset the module and clear
the IRQ pin.
pin this IRQ pin is asserted and the EVLIF bit is
set. This bit must be cleared by software to reset
the module and clear the IRQ pin.
combination of the high and low-speed modules
are enabled.
- 00 – Both modules are off
- 01 – Only low-speed module enabled
- 10 – Only high-speed module disabled
- 11 – Both modules are enabled
the High-Speed Event Detection and allows the
EVHS pin to clear the Watchdog Timer. This is
edge triggered. Either H-L or L-H transition will
clear the WDT.
setting. Depending on the state of this bit the low-
speed pin will have to remain at the same state for
the following periods to be considered valid.
- 0 – 31.25 ms
- 1 – 500 ms
EVENT DETECTION
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Figure
9-7.