MCP795W10-I/SL Microchip Technology, MCP795W10-I/SL Datasheet - Page 33

• Manufacturer Part Number: MCP795W10-I/SL
• Description: SPI GPP RTCC, 1Kb EE, 64B SRAM, WD Timer, Event Detect, ID 14 SOIC .150in TUBE
• Manufacturer: Microchip Technology

9.1.7
The MCP795XXX family of RTCC devices feature a
power-fail time-stamp feature. This feature will save the
time at which V
shown in
must be present and the oscillator must also be run-
ning. There are two separate sets of registers that are
used to record this information:
• The first set located at 0x18h through 0x1Bh are
FIGURE 9-4:
9.1.8
The Read Status Register (SRREAD) instruction pro-
vides access to the STATUS register. The STATUS
register may be read at any time, even during a write
cycle. The STATUS register is formatted as follows:
*
The Write-In-Process (WIP) bit indicates whether the
MCP795XXX is busy with a nonvolatile memory write
operation. When set to a ‘1’, a write is in progress,
when set to a ‘0’, no write is in progress. This bit is
read-only.
The Write Enable Latch (WEL) bit indicates the sta-
tus of the write enable latch. When set to a ‘1’, the
latch allows writes to the nonvolatile memory, when
set to a ‘0’, the latch prohibits writes to the nonvolatile
memory. The state of this bit can always be updated
 2011-2012 Microchip Technology Inc.
loaded at the time when V
and the RTCC operates on the V
(register 0x03h bit 4) bit is also set at this time.
Note:
V
V
—
V
X
7
CC
TRIP(max)
TRIP(min)
Figure
Power-Down
Time-Stamp
— — —
X
6
POWER-FAIL TIME-STAMP
READ STATUS REGISTER
(SRREAD)
Once a Write Status Register is initiated
and a Read Status Register is attempted
the new values for the nonvolatile bits will
be read regardless of whether the values
have been actually programmed into the
device. (i.e., The values are moved to the
latches prior to the write operation).
X
5
CC
9-4. To use this feature, a V
crosses the V
X
4
POWER-FAIL GRAPH
R/W
BP1
3
CC
falls below V
R/W
BP0
2
TRIP
BAT
. The VBAT
voltage and is
WEL
R
1
BAT
TRIP
supply
WIP
MCP795WXX/MCP795BXX
R
0
Preliminary
• The second set of registers, located at 0x1Ch
The power-fail time-stamp registers are cleared when
the VBAT bit is cleared in software.
via the WREN or WRDI commands, regardless of the
state of write protection on the STATUS register. This
bit is read-only.
The Block Protection (BP0 and BP1) bits indicate
which blocks are currently write-protected. These bits
are set by the user issuing the WRSR instruction. These
bits are nonvolatile.
See
through 0x1Fh, are loaded at the time when V
is restored and the RTCC switches to V
Note:
Figure 9-5
It is strongly recommended that the time-
saver function only be used when the
oscillator is running. This will ensure accu-
rate functionality.
for the RDSR timing sequence.
DS22280B-page 33
Time-Stamp
Power-Up
CC
.
CC