STM32W108HBU63TR STMicroelectronics, STM32W108HBU63TR Datasheet
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STM32W108HBU63TR
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STM32W108HBU63TR Summary of contents
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High-performance, IEEE 802.15.4 wireless system-on-chip Features ■ Complete system-on-chip – 32-bit ARM® Cortex™-M3 processor – 2.4 GHz IEEE 802.15.4 transceiver & lower MAC – 128-Kbyte Flash, 8-Kbyte RAM memory – AES128 encryption accelerator – Flexible ADC, SPI/UART/I communications, and general-purpose ...
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Contents Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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STM32W108CB, STM32W108HB 6.2 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Contents 8.3 Debug control and status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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STM32W108CB, STM32W108HB 9.6.3 9.6.4 9.6.5 9.7 Direct memory access (DMA) channels . . . . . . . . . . . . . . . . . . . . . . . . . . 88 9.8 Serial ...
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Contents 9.13.11 Receive DMA end address register B (SCx_RXENDB 103 9.13.12 Receive DMA count register A (SCx_RXCNTA ...
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STM32W108CB, STM32W108HB 10.3.12 Timer x capture/compare 2 register (TIMx_CCR2 153 10.3.13 Timer x capture/compare 3 register (TIMx_CCR3 ...
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Contents 12.2 Event manager . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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STM32W108CB, STM32W108HB 14.9.2 14.9.3 15 Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Description 1 Description The STM32W108 is a fully integrated System-on-Chip that integrates a 2.4 GHz, IEEE 802.15.4-compliant transceiver, 32-bit ARM® Cortex™-M3 microprocessor, Flash and RAM memory, and peripherals of use to designers of 802.15.4-based systems. Figure 1. STM32W108 block diagram ...
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STM32W108CB, STM32W108HB received packets. A packet trace interface is also integrated with the MAC, allowing complete, non-intrusive capture of all packets to and from the STM32W108. The STM32W108 offers a number of advanced power management features that enable long battery ...
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Description 1.2 Overview 1.2.1 Functional description The STM32W108 radio receiver is a low-IF, super-heterodyne receiver. The architecture has been chosen to optimize co-existence with other devices in the 2.4 GHz band (namely, WIFI and Bluetooth), and to minimize power consumption. ...
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STM32W108CB, STM32W108HB GPIO pins will wake up the chip. The STM32W108 has a fast startup time (typically 100 µs) from deep sleep to the execution of the first ARM® Cortex-M3 instruction. The STM32W108 contains three power domains. The always-on high ...
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Documentation conventions 2 Documentation conventions Table 1. Description of abbreviations used for bitfield access Abbreviation Read/Write (rw) Read-only (r) Write only (w) Read/Write in (MPU) Privileged mode only (rws) 1. The conditions under which the hardware (core) sets or clears ...
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STM32W108CB, STM32W108HB 3 Pinout and pin description Figure 2. 48-pin VFQFPN pinout VDD_24MHZ VDD_VCO RF_P RF_N VDD_RF RF_TX_ALT_P RF_TX_ALT_N VDD_IF BIAS_R VDD_PADSA PC5, TX_ACTIVE nRESET ...
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Pinout and pin description Figure 3. 40-pin VFQFPN pinout VDD_VCO RF_P RF_N VDD_RF RF_TX_ALT_P RF_TX_ALT_N VDD_IF BIAS_R VDD_PADSA PC5, TX_ACTIVE Table 2. Pin descriptions 48-Pin 40-Pin Package Package Signal Pin no. Pin no VDD_24MHZ 2 1 VDD_VCO 3 ...
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STM32W108CB, STM32W108HB Table 2. Pin descriptions (continued) 48-Pin 40-Pin Package Package Signal Pin no. Pin no BIAS_R 10 9 VDD_PADSA PC5 11 10 TX_ACTIVE 12 11 nRESET PC6 OSC32B 13 nTX_ACTIVE PC7 14 OSC32A OSC32_EXT 15 12 VREG_OUT ...
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Pinout and pin description Table 2. Pin descriptions (continued) 48-Pin 40-Pin Package Package Signal Pin no. Pin no. PB3 TIM2_CH3 (see Pin 22) UART_CTS 19 15 SC1SCLK PB4 TIM2_CH4 (see also Pin 24 UART_RTS SC1nSSEL 18/209 Direction I/O ...
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STM32W108CB, STM32W108HB Table 2. Pin descriptions (continued) 48-Pin 40-Pin Package Package Signal Pin no. Pin no. PA0 TIM2_CH1 (see also Pin 30 SC2MOSI PA1 TIM2_CH3 (see also Pin 19) SC2SDA 22 18 SC2MISO 23 19 VDD_PADS Direction I/O ...
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Pinout and pin description Table 2. Pin descriptions (continued) 48-Pin 40-Pin Package Package Signal Pin no. Pin no. PA2 TIM2_CH4 (see also Pin 20) SC2SCL 24 20 SC2SCLK PA3 SC2nSSEL TRACECLK (see also Pin 25 21 36) TIM2_CH2 (see also ...
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STM32W108CB, STM32W108HB Table 2. Pin descriptions (continued) 48-Pin 40-Pin Package Package Signal Pin no. Pin no. PA4 ADC4 PTI_EN 26 22 TRACEDATA2 PA5 ADC5 PTI_DATA 27 23 nBOOTMODE TRACEDATA3 28 24 VDD_PADS PA6 29 TIM1_CH3 Direction I/O Digital I/O ADC ...
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Pinout and pin description Table 2. Pin descriptions (continued) 48-Pin 40-Pin Package Package Signal Pin no. Pin no. PB1 SC1MISO SC1MOSI 30 25 SC1SDA SC1TXD TIM2_CH1 (see also Pin 21) 22/209 Direction I/O Digital I/O SPI slave data out of ...
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STM32W108CB, STM32W108HB Table 2. Pin descriptions (continued) 48-Pin 40-Pin Package Package Signal Pin no. Pin no. PB2 SC1MISO SC1MOSI 31 26 SC1SCL SC1RXD TIM2_CH2 (see also Pin 25) SWCLK 32 27 JTCK PC2 JTDO 33 28 SWO Direction I/O Digital ...
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Pinout and pin description Table 2. Pin descriptions (continued) 48-Pin 40-Pin Package Package Signal Pin no. Pin no. PC3 34 29 JTDI PC4 JTMS 35 30 SWDIO PB0 VREF VREF 36 IRQA TRACECLK (see also Pin 25) TIM1CLK TIM2MSK 37 ...
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STM32W108CB, STM32W108HB Table 2. Pin descriptions (continued) 48-Pin 40-Pin Package Package Signal Pin no. Pin no. PC1 ADC3 SWO (see also Pin 38 31 33) TRACEDATA0 39 32 VDD_MEM PC0 JRST 40 33 (1) IRQD TRACEDATA1 PB7 ADC2 41 34 ...
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Pinout and pin description Table 2. Pin descriptions (continued) 48-Pin 40-Pin Package Package Signal Pin no. Pin no. PB6 ADC1 42 35 IRQB TIM1_CH1 PB5 ADC0 43 TIM2CLK TIM1MSK 44 36 VDD_CORE 45 37 VDD_PRE 46 VDD_SYNTH 47 38 OSCB ...
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STM32W108CB, STM32W108HB 4 Embedded memory Figure 4. STM32W108 memory mapping 0xE00FFFFF 0xE00FF000 0xE0042000 0xE0041000 0xE0040000 0xE003FFFF 0xE000F000 0xE000E000 0xE0003000 0xE0002000 0xE0001000 0xE0000000 0x42002XXX 0x42000000 0x40000XXX 0x40000000 0x22002000 0x22000000 0x20001FFF 0x20000000 0x080409FF Customer Info Block (0.5kB) 0x08040800 0x080407FF 0x08040000 0x0801FFFF 0x08000000 ...
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Embedded memory 4.1 Flash memory The STM32W108 provides a total of 130.5 kB Kbytes of Flash memory in three separate blocks: ● Main Flash Block (MFB) ● Fixed Information Block (FIB) ● Customer Information Block (CIB) The MFB is divided ...
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STM32W108CB, STM32W108HB 6. Serial Controller 1 Transmit 4.2.2 RAM memory protection The STM32W108 integrates two memory protection mechanisms. The first memory protection mechanism is through the ARM® Cortex-M3 Memory Protection Unit (MPU) described in the Memory Protection Unit section. The ...
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Radio frequency module 5 Radio frequency module The radio module consists of an analog front end and digital baseband as shown in Figure 1: STM32W108 block 5.1 Receive (Rx) path The Rx path uses a low-IF, super-heterodyne receiver that rejects ...
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STM32W108CB, STM32W108HB 5.2.1 Tx baseband The STM32W108 Tx baseband in the digital domain spreads the 4-bit symbol into its IEEE 802.15.4-2003-defined 32-chip sequence. It also provides the interface for software to calibrate the Tx module to reduce silicon process, temperature, ...
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Radio frequency module The primary features of the MAC are: ● CRC generation, appending, and checking ● Hardware timers and interrupts to achieve the MAC symbol timing ● Automatic preamble and SFD pre-pending on Tx packets ● Address recognition and ...
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STM32W108CB, STM32W108HB 6 System modules System modules encompass power, resets, clocks, system timers, power management, and encryption. Figure 5 Figure 5. System module block diagram recomended connections for internal regulator External Regulator optional connections for external regulator shows these modules ...
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System modules 6.1 Power domains The STM32W108 contains three power domains: ● An "always on domain" containing all logic and analog cells required to manage the STM32W108's power modes, including the GPIO controller and sleep timer. This domain must remain ...
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STM32W108CB, STM32W108HB 6.2 Resets The STM32W108 resets are generated from a number of sources. Each of these reset sources feeds into central reset detection logic that causes various parts of the system to be reset depending on the state of ...
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System modules Deep sleep reset The Power Management module informs the Reset Generation module of entry into and exit from the deep sleep states. The deep sleep reset is applied in the following states: before entry into deep sleep, while ...
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STM32W108CB, STM32W108HB ● PRESETHV ● PRESETLV Table 3 shows which reset sources generate certain resets. Table 3. Generated resets Reset source POR HV POR LV (in deep sleep) POR LV (not in deep sleep) RSTB Watchdog reset Software reset Option ...
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System modules Bit 4 SW_RST: When set to ‘1’, the reset is due to a software reset. Bit 3 W_DOG: When set to ‘1’, the reset is due to watchdog expiration. Bit 2 RSTB_PIN: When set to ‘1’, the reset ...
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STM32W108CB, STM32W108HB Figure 6 shows a block diagram of the clocks in the STM32W108. This simplified view shows all the clock sources and the general areas of the chip to which they are routed. Figure 6. Clocks block diagram 12MHz ...
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System modules calibrated accuracy of OSCHF is ±250 kHz ±40 ppm. The UART and ADC peripherals may not be usable due to the lower accuracy of the OSCHF frequency. See also Section 14.5.1: High frequency internal clock characteristics on page ...
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STM32W108CB, STM32W108HB In addition to these modes, further automatic control is invoked by hardware when flash programming is enabled. To ensure accuracy of the flash controller's timers, the FCLK frequency is forced to 12 MHz during flash programming and erase ...
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System modules Bit 0 CPU_CLK_SEL: When set to ‘0’, 12-MHz CPU clock is selected. When set to ‘1’, 24-MHz CPU clock is selected. Note that the clock selection also determines if RAM controller is running at the same speed as ...
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STM32W108CB, STM32W108HB 6.4.3 Event timer The SysTick timer is an ARM® standard system timer in the NVIC. The SysTick timer can be clocked from either the FCLK (the clock going into the CPU) or the Sleep Timer clock. FCLK is ...
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System modules Watchdog restart register (WDOG_RESTART) Write any value to this register to kick-start the watchdog. Address: Reset value: Sleep timer configuration register (SLEEPTMR_CFG) This register sets the various options for the Sleep timer. Address: Reset value ...
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STM32W108CB, STM32W108HB Bits [15:0] SLEEPTMR_CNTH_FIELD: Sleep timer counter high value [31:16]. Reading this register updates the SLEEP_COUNT_L for subsequent reads. Sleep timer count low register (SLEEPTMR_CNTL) Address: Reset value ...
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System modules Sleep timer compare A low register (SLEEPTMR_CMPAL) Address: Reset value Bits [15:0] SLEEPTMR_CMPAL_FIELD: Sleep timer compare A low value [15:0]. Writing to this register puts value in hold ...
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STM32W108CB, STM32W108HB Sleep timer compare B low register (SLEEPTMR_CMPBL) Address: Reset value Bits [15:0] SLEEPTMR_CMPBL_FIELD: Sleep timer compare B low value [15:0]. Writing to this register puts value in hold ...
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System modules Sleep timer interrupt mask register (INT_SLEEPTMRCFG) Address: 0x4000 A054 Reset value Bit 2 INT_ SLEEPTMR CMPB: Sleep timer compare B Bit 1 INT_SLEEPTMRCMPA: Sleep timer compare A Bit ...
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STM32W108CB, STM32W108HB 6.5 Power management The STM32W108's power management system is designed to achieve the lowest deep sleep current consumption possible while still providing flexible wakeup sources, timer activity, and debugger operation. The STM32W108 has four main sleep modes: ● ...
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System modules 6.5.2 Basic sleep modes The power management state diagram in management controller. Figure 7. Power management state diagram DEEP SLEEP PRE- DEEP SLEEP CSYSPWRUPREQ & INHIBIT 50/209 STM32W108CB, STM32W108HB Figure 7 shows the basic operation of the power ...
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STM32W108CB, STM32W108HB In normal operation an application may request one of two low power modes through program execution: ● Idle Sleep is achieved by executing a WFI instruction whilst the SLEEPDEEP bit in the Cortex System Control register (SCS_SCR) is ...
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System modules initiates access while the STM32W108 is in deep sleep, the SWJ intelligently holds off the debugger for a brief period of time until the STM32W108 is properly powered and ready. For more information regarding the SWJ and the ...
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STM32W108CB, STM32W108HB 7 Integrated voltage regulator The STM32W108 integrates two low dropout regulators to provide 1.8 V and 1.25 V power supplies. The 1V8 regulator supplies the analog and memories, and the 1V25 regulator supplies the digital core. In deep ...
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Integrated voltage regulator Table 5. 1.8 V integrated voltage regulator specifications (continued) Parameter 1V8 regulator start-up time 1V25 regulator start-up time An external 1.8 V regulator may replace both internal regulators. The STM32W108 can control external regulators during deep sleep ...
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STM32W108CB, STM32W108HB 8 General-purpose input/outputs The STM32W108 has 24 multi-purpose GPIO pins that may be individually configured as: ● General purpose output ● General purpose open-drain output ● Alternate output controlled by a peripheral device ● Alternate open-drain output controlled ...
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General-purpose input/outputs 8.1 Functional description 8.1.1 GPIO ports The 24 GPIO pins are grouped into three ports: PA, PB, and PC. Individual GPIOs within a port are numbered according to their bit positions within the GPIO registers. ...
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STM32W108CB, STM32W108HB Table 6. GPIO configuration modes (continued) GPIO mode Alternate Output (open- drain) Alternate Output (push- pull) SPI SCLK Mode If a GPIO has two peripherals that can be the source of alternate output mode data, then other registers ...
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General-purpose input/outputs Table 8. GPIO forced functions GPIO GPIO_EXTREGEN bit set in the PA7 GPIO_DBGCFG register PC0 Debugger interface is active in JTAG mode PC2 Debugger interface is active in JTAG mode PC3 Debugger interface is active in JTAG mode ...
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STM32W108CB, STM32W108HB 8.1.6 GPIO modes Analog mode Analog mode enables analog functions, and disconnects a pin from the digital input and output logic. Only the following GPIO pins have analog functions: ● PA4, PA5, PB5, PB6, PB7, and PC1 can ...
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General-purpose input/outputs When configured in output mode: ● The output drivers are enabled and are controlled by the value written to GPIO_PxOUT: ● In open-drain mode: 0 activates the N-MOS current sink; 1 tri-states the pin. ● In push-pull mode: ...
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STM32W108CB, STM32W108HB activity caused a wake event, but not which specific GPIO was responsible. Instead, software should read the state of the GPIOs on waking to determine the cause of the event. The register GPIO_WAKEFILT contains bits to enable digital ...
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General-purpose input/outputs Table 9. IRQC/D GPIO selection (continued) GPIO_IRQxSEL some cases, it may be useful to assign IRQC or IRQD to an input also in use by a peripheral, for example to generate an interrupt from ...
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STM32W108CB, STM32W108HB Table 10. GPIO signal assignments (continued) GPIO PB1 PB2 PB3 PB4 PB5 PB6 PB7 PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 1. Default signal assignment (not remapped). 2. Overrides during reset as an input with pull up. ...
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General-purpose input/outputs 8.5 General-purpose input / output (GPIO) registers 8.5.1 Port x configuration register (Low) ( Address offset: 0xB000 (GPIO_PACFGL), 0xB400 (GPIO_PBCFGL) and 0xB800 (GPIO_PCCFGL) Reset value Px3_CFG rw Bits ...
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STM32W108CB, STM32W108HB Bits [15:12] Px7_CFG: GPIO configuration control. 0x0: Analog, input or output (GPIO_PxIN always reads 1). 0x1: Output, push-pull (GPIO_PxOUT controls the output). 0x4: Input, floating. 0x5: Output, open-drain (GPIO_PxOUT controls the output). 0x8: Input, pulled up or down ...
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General-purpose input/outputs Reserved Bit 7 Px7: Output data for Px7. Bit 6 Px6: Output data for Px6. Bit 5 Px5: Output data for Px5. Bit 4 Px4: Output data for Px4. Bit 3 Px3: Output ...
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STM32W108CB, STM32W108HB 8.5.6 Port x output set register (GPIO_PxSET) Address offset: 0xB010 (GPIO_PASET), 0xB410 (GPIO_PBSET) Reset value Reserved Bits [15:8] Reserved: these bits must be set to 0. Bit 7 ...
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General-purpose input/outputs Bit 2 Px2: Write 1 to enable wakeup monitoring of Px2. Bit 1 Px1: Write 1 to enable wakeup monitoring of Px1. Bit 0 Px0: Write 1 to enable wakeup monitoring of Px0. 8.5.8 GPIO wakeup filtering register ...
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STM32W108CB, STM32W108HB Bits [4:0] SEL_GPIO: Pin assigned to IRQx. 0x00: PA0. 0x01: PA1. 0x02: PA2. 0x03: PA3. 0x04: PA4. 0x05: PA5. 0x06: PA6. 0x07: PA7. 0x08: PB0. 0x09: PB1. 0x0A: PB2. 0x0B: PB3. 0x0C: PB4. 8.5.10 GPIO interrupt x configuration ...
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General-purpose input/outputs Bit 3 INT_IRQDFLAG: IRQD interrupt pending. Bit 2 INT_IRQCFLAG: IRQC interrupt pending. Bit 1 INT_IRQBFLAG: IRQB interrupt pending. Bit 0 INT_IRQAFLAG: IRQA interrupt pending. 8.5.12 GPIO debug configuration register (GPIO_DBGCFG) Address offset: 0xBC00 ...
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STM32W108CB, STM32W108HB Bit 3 GPIO_BOOTMODE: The state of the nBOOTMODE signal sampled at the end of reset. 0: nBOOTMODE was not asserted (it read high). 1: nBOOTMODE was asserted (it read low). Bit 1 GPIO_FORCEDBG: ...
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Serial interfaces 9 Serial interfaces 9.1 Functional description The STM32W108 has two serial controllers, SC1 and SC2, which provide several options for full-duplex synchronous and asynchronous serial communications. ● SPI (Serial Peripheral Interface), master or slave 2 ● ...
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STM32W108CB, STM32W108HB Figure 9. Serial controller block diagram SCx Interrupt SCx_MODE SCx TX DMA channel SCx RX DMA channel 9.2 Configuration Before using a serial controller, it should be configured and initialized as follows: 1. Set up the parameters specific ...
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Serial interfaces Table 11. SC1 GPIO usage and configuration Interface SC1MOSI alternate SPI - Master output (push-pull) SC1MISO alternate SPI - Slave output (push-pull) SC1SDA alternate Master output (open-drain) TXD alternate UART output (push-pull) 1. used ...
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STM32W108CB, STM32W108HB Table 13. SPI master GPIO usage Parameter Direction GPIO configuration SC1 pin SC2 pin 9.3.1 Setup and configuration Both serial controllers, SC1 and SC2, support SPI master mode. SPI master mode is enabled by the following register settings: ...
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Serial interfaces Table 14. SPI master mode formats (continued) SCx_SPICFG (1) SC_SPIxxx MST ORD PHA POL Same as above except data is sent LSB first instead of MSB ...
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STM32W108CB, STM32W108HB Every time an automatic character transmission starts, a transmit underrun is detected as there is no data in transmit FIFO, and the INT_SCTXUND bit in the INT_SC2FLAG register is set. After automatic character transmission is disabled, no more ...
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Serial interfaces Table 15. SPI slave GPIO usage Parameter Direction GPIO configuration SC1 pin SC2 pin 9.4.1 Setup and configuration Both serial controllers, SC1 and SC2, support SPI slave mode. SPI slave mode is enabled by the following register settings: ...
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STM32W108CB, STM32W108HB Table 16. SPI slave mode formats (continued) SCx_SPICFG (1) SC_SPIxxx MST ORD PHA POL nSSEL SCLK MOSI in MISO out Same as above except LSB first instead of MSB ...
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Serial interfaces The SPI slave controller must guarantee that there is time to move new transmit data from the transmit FIFO into the hardware serializer. To provide sufficient time, the SPI slave controller inserts a byte of padding at the ...
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STM32W108CB, STM32W108HB 2 The I C master controller uses just two signals: ● SDA (Serial Data) - bidirectional serial data ● SCL (Serial Clock) - bidirectional serial clock Table 17 lists the GPIO pins used by the SC1 and SC2 ...
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Serial interfaces 2 Table 19 master frame segments SCx_TWICTRL1 (1) SC_TWIxxxx START SEND RECV STOP ...
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STM32W108CB, STM32W108HB receive frame segment is determined with the SC_TWIACK bit in the SCx_TWICTRL2 register. 2 Figure 10 segment transitions Generation of a 7-bit address is accomplished with one transmit segment. The upper 7 bits of the ...
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Serial interfaces 9.5.3 Interrupts master controller interrupts are generated on the following events: ● Bus command (SC_TWISTART/SC_TWISTOP) completed ( transition of SC_TWICMDFIN) ● Character transmitted and slave device responded with NACK ● Character transmitted (0 ...
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STM32W108CB, STM32W108HB 9.6.1 Setup and configuration The UART baud rate clock is produced by a programmable baud generator starting from the 24 Hz clock: The integer portion of the divisor written to the SC1_UARTPER register and the fractional ...
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Serial interfaces A UART character frame contains, in sequence: ● The start bit ● The least significant data bit ● The remaining data bits ● If parity is enabled, the parity bit ● The stop bit, or bits ...
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STM32W108CB, STM32W108HB Figure 13. RTS/CTS flow control connections UART Transmitter The UART RTS/CTS flow control options are selected by the SC1_UARTFLOW and SC1_UARTAUTO bits in the SC1_UARTCFG register (see SC1_UARTFLOW bit is set, the UART will not start transmitting a ...
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Serial interfaces offset is 4 characters ahead of the actual overflow at the input to the receive FIFO. Two conditions will clear the error indication: setting the appropriate SC_RXDMARST bit in the SC1_DMACTRL register, or loading the appropriate DMA buffer ...
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STM32W108CB, STM32W108HB ● Enable top level NVIC interrupts by setting the INT_SCx bit in the INT_CFGSET register. ● Start the DMA by loading the DMA buffers by setting the SC_TXLODA/B (or SC_RXLODA/B) bits in the SCx_DMACTRL register. A DMA buffer's ...
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Serial interfaces 9.8.2 Serial controller interrupt flag register (INT_SCxFLAG) Address offset: 0xA808 (INT_SC1FLAG) and 0xA80C (INT_SC2FLAG) Reset value INT_S INT_S INT_S INT_S C1PA C1FR CTXU CTXU Reser RERR MERR LDB ...
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STM32W108CB, STM32W108HB Bit 14 INT_SC1PARERR: Parity error received (UART) interrupt enable. Bit 13 INT_SC1FRMERR: Frame error received (UART) interrupt enable. Bit 12 INT_SCTXULDB: DMA transmit buffer B unloaded interrupt enable. Bit 11 INT_SCTXULDA: DMA transmit buffer A unloaded interrupt enable. ...
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Serial interfaces 9.9 SPI master mode registers 9.9.1 Serial data register (SCx_DATA) Address offset: 0xC83C (SC1_DATA) and 0xC03C (SC2_DATA) Reset value Reserved Bits [7:0] SC_DATA: Transmit and receive data register. ...
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STM32W108CB, STM32W108HB Bit 1 SC_SPIPHA: Clock phase configuration: clear this bit to sample on the leading (first edge) and set this bit to sample on the second edge. Bit 0 SC_SPIPOL: Clock polarity configuration: clear this bit for a rising ...
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Serial interfaces 9.9.5 Serial clock exponential prescaler register (SCx_RATEEXP) Address offset: 0xC864 (SC1_RATEEXP) and 0xC064 (SC2_RATEEXP) Reset value Bits [3:0] SC_RATEEXP: The exponential component (EXP) of the clock rate in ...
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STM32W108CB, STM32W108HB 2 9.11 control 1 register (SCx_TWICTRL1) Address offset: 0xC84C (SC1_TWICTRL1) and 0xC04C (SC2_TWICTRL1) Reset value Bit 3 SC_TWISTOP: Setting this bit sends the STOP command. It ...
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Serial interfaces 9.12 Universal asynchronous receiver / transmitter (UART) registers Refer to the SPI Master mode section for a description of the SCx_DATA register. 9.12.1 UART status register (SC1_UARTSTAT) Address offset: 0xC848 Reset value ...
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STM32W108CB, STM32W108HB Bit 6 SC_UARTAUTO: Set this bit to enable automatic nRTS control by hardware (SC_UARTFLOW must also be set). When automatic control is enabled, nRTS will be deasserted when the receive FIFO has space for only one more byte ...
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Serial interfaces Bits [0] SC_UARTFRAC: The fractional part of the baud rate period (F) in the equation: Rate = 24 MHz / ( ( 9.13 DMA channel registers 9.13.1 Serial ...
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STM32W108CB, STM32W108HB Bit 1 SC_RXLODB: Setting this bit loads DMA receive buffer B addresses and allows the DMA controller to start processing receive buffer B. If both buffer A and B are loaded simultaneously, buffer A will be used first. ...
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Serial interfaces Bit 6 This bit is set when DMA receive buffer A reads a byte with a parity error from the receive FIFO cleared the next time buffer A is loaded or when the receive DMA is ...
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STM32W108CB, STM32W108HB Bits [12:0] SC_TXBEGA: DMA transmit buffer B start address. 9.13.5 Transmit DMA end address register A (SCx_TXENDA) Address offset: 0xC814 (SC1_TXENDA) and 0xC014 (SC2_TXENDA) Reset value Reserved Bits ...
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Serial interfaces Bits [12:0] SC_TXCNT: The offset from the start of the active DMA transmit buffer from which the next byte will be read. This register is set to zero when the buffer is loaded and when the DMA is ...
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STM32W108CB, STM32W108HB Bits [12:0] SC_RXENDA: Address of the last byte that will be written in the DMA receive buffer A. 9.13.11 Receive DMA end address register B (SCx_RXENDB) Address offset: 0xC80C (SC1_RXENDB) and 0xC00C (SC2_RXENDB) Reset value ...
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Serial interfaces Bits [12:0] SC_RXCNTB: The offset from the start of DMA receive buffer B at which the next byte will be written. This register is set to zero when the buffer is loaded and when the DMA is reset. ...
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STM32W108CB, STM32W108HB Reserved Bits [12:0] SC_RXERRB: The offset from the start of DMA receive buffer B of the first byte received with a parity, frame, or overflow error. Note that an overflow error occurs at ...
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General-purpose timers 10 General-purpose timers Each of the STM32W108's two general-purpose timers consists of a 16-bit auto-reload counter driven by a programmable prescaler. They may be used for a variety of purposes, including measuring the pulse lengths of input signals ...
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STM32W108CB, STM32W108HB Figure 14. General-purpose timer block diagram Note: The internal signals shown in descriptions on page 137 components are interconnected. 10.1 Functional description The timers can optionally use GPIOs in the PA and PB ports for external inputs or ...
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General-purpose timers The GPIOs that can be used by Timer 1 are fixed, but the GPIOs that can be used as Timer 2 channels can be mapped to either of two pins, as shown in Register (TIM2_OR) has four single ...
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STM32W108CB, STM32W108HB Note: When the STM32W108 enters debug mode and the ARM® Cortex-M3 core is halted, the counters continue to run normally. Prescaler The prescaler can divide the counter clock frequency by power of two from 1 through 32768. It ...
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General-purpose timers When an update event occurs, the update flag (the INT_TIMUIF bit in the INT_TIMxFLAG register) is set (unless TIM_USR is 1) and the following registers are updated: ● The buffer of the prescaler is reloaded with the buffer ...
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STM32W108CB, STM32W108HB Figure 18. Counter timing diagram, update event when TIM_ARBE = 0 (TIMx_ARR not buffered) Figure 19. Counter timing diagram, update event when TIM_ARBE = 1 (TIMx_ARR buffered) Down-counting mode In down-counting mode, the counter counts from the auto-reload ...
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General-purpose timers reload value, whereas the prescalar's counter restarts from 0, but the prescale rate doesn't change. In addition, if the TIM_URS bit in the TIMx_CR1 register is set, setting the TIM_UG bit generates an update event, but without setting ...
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STM32W108CB, STM32W108HB autoreload value down to 1 and generates a counter underflow event. Then it restarts counting from 0. In this mode, the direction bit (TIM_DIR in the TIMx_CR1 register) cannot be written updated by hardware and gives ...
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General-purpose timers Figure 23. Counter timing diagram, update event with TIM_ARBE = 1 (counter underflow) Figure 24. Counter timing diagram, update event with TIM_ARBE = 1 (counter overflow) 114/209 STM32W108CB, STM32W108HB Doc ID 16252 Rev 8 ...
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STM32W108CB, STM32W108HB 10.1.3 Clock selection The counter clock can be provided by the following clock sources: ● Internal clock (PCLK) ● External clock mode 1: external input pin (TIy) ● External clock mode 2: external trigger input (ETR) ● Internal ...
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General-purpose timers Figure 26. TI2 external clock connection example For example, to configure the up-counter to count in response to a rising edge on the TI2 input, use the following procedure: 1. Configure channel 2 to detect rising edges on ...
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STM32W108CB, STM32W108HB External clock source mode 2 This mode is selected by writing TIM_ECE = 1 in the TIMx_SMCR register. The counter can count at each rising or falling edge on the external trigger input ETR. The TIM_EXTRIGSEL bits in ...
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General-purpose timers Figure 29. Control circuit in external clock mode 2 10.1.4 Capture/compare channels Each capture/compare channel is built around a capture/compare register including a shadow register, an input stage for capture with digital filter, multiplexing and prescaler, and an ...
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STM32W108CB, STM32W108HB Figure 31. Capture/compare channel 1 main circuit Figure 32. Output stage of capture/compare channel (channel 1) The capture/compare block is made of a buffer register and a shadow register. Writes and reads always access the buffer register. In ...
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General-purpose timers cleared by software writing its bit or reading the captured data stored in the TIMx_CCRy register. To clear the INT_TIMMISSCCyIF bit, write it. The following example shows how to capture the counter ...
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STM32W108CB, STM32W108HB For example, to measure the period in the TIMx_CCR1 register and the duty cycle in the TIMx_CCR2 register of the PWM applied on TI1, use the following procedure depending on CK_INT frequency and prescaler value: ● Select the ...
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General-purpose timers The OCyREF signal can be forced low by writing the TIM_OCyM bits to 100 in the TIMx_CCMR1 register. The comparison between the TIMx_CCRy shadow register and the counter is still performed and allows the INT_TIMxCCRyIF flag to be ...
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STM32W108CB, STM32W108HB Figure 34. Output compare mode, toggle on OC1 10.1.9 PWM mode Pulse width modulation mode allows you to generate a signal with a frequency determined by the value of the TIMx_ARR register, and a duty cycle determined by ...
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General-purpose timers PWM edge-aligned mode: up-counting configuration Up-counting is active when the TIM_DIR bit in the TIMx_CR1 register is low. Refer to counting mode on page The following example uses PWM mode 1. The reference PWM signal OCyREF is high ...
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STM32W108CB, STM32W108HB Figure 36 shows some center-aligned PWM waveforms in an example where: ● TIMx_ARR = 8, ● PWM mode is the PWM mode 1, ● The output compare flag is set when the counter counts down corresponding to the ...
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General-purpose timers ● The direction is not updated the value written to the counter that is greater than the auto-reload value (TIMx_CNT > TIMx_ARR). For example, if the counter was counting up, it continues to count up. ● The direction ...
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STM32W108CB, STM32W108HB For example, to generate a positive pulse on OC1 with a length of tPULSE and after a delay of tDELAY as soon as a rising edge is detected on the TI2 input pin, using TI2FP2 as trigger 1: ...
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General-purpose timers filtered and not inverted.) The sequence of transitions of the two inputs is evaluated, and generates count pulses as well as the direction signal. Depending on the sequence, the counter counts up or down, and hardware modifies the ...
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STM32W108CB, STM32W108HB Figure 38. Example of counter operation in encoder interface mode Figure 39 gives an example of counter behavior when IC1FP1 polarity is inverted (same configuration as above except TIM_CC1P = 1). Figure 39. Example of encoder interface mode ...
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General-purpose timers The XOR output can be used with all the timer input functions such as trigger or input capture especially useful to interface to Hall effect sensors. 10.1.13 Timers and external trigger synchronization The timers can be ...
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STM32W108CB, STM32W108HB Slave mode: Gated mode In Gated mode the counter is enabled depending on the level of a selected input. In the following example, the up-counter counts only when the TI1 input is low: ● Configure channel 1 to ...
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General-purpose timers The delay between the rising edge on TI2 and the actual start of the counter is due to the resynchronization circuit on the TI2 input. Figure 42. Control circuit in Trigger mode Slave mode: External clock mode 2 ...
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STM32W108CB, STM32W108HB Figure 43. Control circuit in External clock mode 2 + Trigger mode 10.1.14 Timer synchronization The two timers can be linked together internally for timer synchronization or chaining. A timer configured in Master mode can reset, start, stop ...
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General-purpose timers Using one timer to enable the other timer In this example, the enable of Timer 2 is controlled with the output compare 1 of Timer 1. Refer to Figure 44 OC1REF of Timer 1 is high. Both counter ...
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STM32W108CB, STM32W108HB ● Reset Timer 2 by writing 1 in the TIM_UG bit (TIM2_EGR register). ● Initialize Timer 2 to 0xE7 by writing 0xE7 in the Timer 2 counter (TIM2_CNTL). ● Enable Timer 2 by writing 1 in the TIM_CEN ...
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General-purpose timers Figure 47. Triggering timer 2 with update of Timer the previous example, both counters can be initialized before starting counting. Figure 46 shows the behavior with the same configuration shown in mode instead of gated ...
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STM32W108CB, STM32W108HB ● Configure the Timer 1 in master/slave mode by writing TIM_MSM = 1 (TIM1_SMCR register). ● Configure Timer 2 to get the input trigger from Timer 1 (TIM_TS = 000 in the TIM2_SMCR register). ● Configure Timer 2 ...
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General-purpose timers Table 26. Timer signal descriptions (continued) Signal ICyPS ITR0 OCy OCyREF PCLK TIy TIyFPy TIMxCy TIMxCLK TIMxMSK TRGI 10.2 Interrupts Each timer has its own ARM® Cortex-M3 vectored interrupt with programmable priority. Writing 1 to the INT_TIMx bit ...
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STM32W108CB, STM32W108HB 10.3 General-purpose timer (1 and 2) registers 10.3.1 Timer x control register 1 (TIMx_CR1) Address offset: 0xE000 (TIM1) and 0xF000 (TIM2) Reset value Reserved Bit 7 TIM_ARBE: Auto-Reload ...
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General-purpose timers Bit 1 TIM_UDIS: Update Disable 0: An update event is generated as soon as a counter overflow occurs, a software update is generated hardware reset is generated by the slave mode controller. Shadow registers are then ...
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STM32W108CB, STM32W108HB Bits [6:4] TIM_MMS: Master Mode Selection This selects the information to be sent in master mode to a slave timer for synchronization using the trigger output (TRGO). 000: Reset - the TIM_UG bit in the TMRx_EGR register is ...
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General-purpose timers Bit 14 TIM_ECE: External Clock Enable This bit enables external clock mode 2. 0: External clock mode 2 disabled. 1: External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal. Note: ...
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STM32W108CB, STM32W108HB Bits [2:0] TIM_SMS: Slave Mode Selection When external signals are selected the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input. 000: Slave mode disabled. If TIM_CEN = 1 then ...
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General-purpose timers Bit 6 TIM_TG: Trigger Generation 0: Does nothing. 1: Sets the TIM_TIF flag in the INT_TIMxFLAG register. Bit 4 TIM_CC4G: Capture/Compare 4 Generation 0: Does nothing CC4 configured as output channel: The TIM_CC4IF flag is set. ...
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STM32W108CB, STM32W108HB 10.3.5 Timer x capture/compare mode register 1 (TIMx_CCMR1) Address offset: 0xE018 (TIM1) and 0xF018 (TIM2) Reset value TIM_O TIM_OC2M C2BE TIM_IC2F TIM_IC2PSC Timer ...
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General-purpose timers Bit 10 TIM_OC2FE: Output Compare 2 Fast Enable. (Applies only if TIM_CC2S = 0) This bit speeds the effect of an event on the trigger in input on the OC2 output. 0: OC2 behaves normally depending on the ...
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STM32W108CB, STM32W108HB Bits [1:0] TIM_CC1S: Capture / Compare 1 Selection This configures the channel as an output or an input input, it selects the input source. 00: Channel is an output. 01: Channel is an input and is ...
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General-purpose timers Bits [14:12] TIM_OC4M: Output Compare 4 Mode. (Applies only if TIM_CC4S = 0 Define the behavior of the output reference signal OC4REF from which OC4 derives. OC4REF is active high whereas OC4’s active level depends on the TIM_CC4P ...
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STM32W108CB, STM32W108HB Bits [15:12] TIM_IC4F: Input Capture 1 Filter. (Applies only if TIM_CC4S > 0) This defines the frequency used to sample the TI4 input, f filter applied to TI4. The digital filter requires N consecutive samples in the same ...
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General-purpose timers Bits [1:0] TIM_CC3S: Capture / Compare 3 Selection This configures the channel as an output or an input input, it selects the input source. 00: Channel is an output. 01: Channel is an input and is ...
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STM32W108CB, STM32W108HB Bit 5 TIM_CC2P Refer to the CC4P description above. Bit 4 TIM_CC2E Refer to the CC43 description above. Bit 1 TIM_CC1P Refer to the CC4P description above. Bit 0 TIM_CC1E Refer to the CC4E description above. 10.3.8 Timer ...
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General-purpose timers 10.3.10 Timer x auto-reload register (TIMx_ARR) Address offset: 0xE02C (TIM1) and 0xF02C (TIM2) Reset value Bits [15:0] TIM_ARR: Auto-reload value TIM_ARR is the value to be loaded in ...
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STM32W108CB, STM32W108HB 10.3.12 Timer x capture/compare 2 register (TIMx_CCR2) Address offset: 0xE038 (TIM1) and 0xF038 (TIM2) Reset value Bits [15:0] See description in the TIMx_CCR1 register. 10.3.13 Timer x capture/compare ...
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General-purpose timers 10.3.15 Timer 1 option register (TIM1_OR) Address offset: 0xE050 Reset value Bit 3 TIM_ORRSVD Reserved: this bit must always be set to 0. Bit 2 TIM_CLKMSKEN Enables TIM1MSK ...
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STM32W108CB, STM32W108HB Bit 3 TIM_ORRSVD Reserved: this bit must always be set to 0. Bit 2 TIM_CLKMSKEN Enables TIM2MSK when TIM2CLK is selected as the external trigger TIM2MSK not used TIM2CLK is ANDed with the TIM2MSK ...
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General-purpose timers Bits [12:9] INT_TIMRSVD: May change during normal operation. Bit 6 INT_TIMTIF: Trigger interrupt. Bit 4 INT_TIMCC4IF: Capture or compare 4 interrupt pending. Bit 3 INT_TIMCC3IF: Capture or compare 3 interrupt pending. Bit 2 INT_TIMCC2IF: Capture or compare 2 ...
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STM32W108CB, STM32W108HB 11 Analog-to-digital converter The STM32W108 analog-to-digital converter (ADC first-order sigma-delta converter with the following features: ● Resolution bits ● Sample times as fast as 5.33 µs (188 kHz) ● Differential and single-ended ...
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Analog-to-digital converter 11.1 Functional description 11.1.1 Setup and configuration To use the ADC follow this procedure, described in more detail in the next sections: ● Configure any GPIO pins to be used by the ADC in analog mode. ● Configure ...
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STM32W108CB, STM32W108HB 11.1.4 Offset/gain correction When a conversion is complete, the 16-bit converted data is processed by offset/gain correction logic: ● The basic ADC conversion result is added to the 16-bit signed (two’s complement) value of the ADC offset register ...
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Analog-to-digital converter 11.1.6 ADC configuration register The ADC configuration register (ADC_CFG) sets up most of the ADC operating parameters. Input The analog input of the ADC can be chosen from various sources. The analog input is configured with the ADC_MUXP ...
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STM32W108CB, STM32W108HB Table 29. Typical ADC input configurations (continued) ADC P input ADC5 GND VREF VDD_PADSA/2 Input range ADC inputs can be routed through input buffers to expand the input voltage range. The input buffers have a fixed 0.25 gain ...
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Analog-to-digital converter Table 30. ADC sample times (continued) Sample ADC_PERIOD clocks 6 7 Note: ADC sample timing is the same whether the STM32W108 is using the 24 MHz crystal oscillator or the 12 MHz high-speed RC oscillator. This facilitates using ...
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STM32W108CB, STM32W108HB To convert multiple inputs using this approach, repeat Steps 4 through 6, loading the desired input configurations to ADC_CFG in Step 5. If the inputs can use the same offset/gain correction, just repeat Steps 5 and 6. 11.1.8 ...
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Analog-to-digital converter 11.2 Interrupts The ADC has its own ARM ADC interrupt is enabled by writing the INT_ADC bit to the INT_CFGSET register, and cleared by writing the INT_ADC bit to the INT_CFGCLR register. page 170 describes the interrupt system ...
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STM32W108CB, STM32W108HB Bits [15:13] ADC_PERIOD: ADC sample time in clocks and the equivalent significant bits in the conversion clocks (5 bits).4: 512 clocks (9 bits clocks (6 bits).5: 1024 clocks (10 bits). 2: 128 clocks (7 ...
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Analog-to-digital converter 11.3.3 ADC gain register (ADC_GAIN) Address offset: 0xD00C Reset value Bits [15:0] ADC_GAIN_FIELD: Gain factor that is multiplied by the offset-corrected ADC result to produce the output value. ...
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STM32W108CB, STM32W108HB 11.3.5 ADC DMA status register (ADC_DMASTAT) Address offset: 0xD014 Reset value Bit 1 ADC_DMAOVF: DMA overflow: occurs when an ADC result is ready and the DMA is not ...
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Analog-to-digital converter Bits [11:0] ADC_DMASIZE_FIELD: ADC buffer size. This is the number of 16-bit ADC conversion results the buffer can hold, not its length in bytes. (The length in bytes is twice this value.) 11.3.8 ADC DMA current address register ...
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STM32W108CB, STM32W108HB 11.3.10 ADC interrupt flag register (INT_ADCFLAG) Address offset: 0xA810 Reset value Bit 4 INT_ADCOVF: DMA buffer overflow interrupt pending. Bit 3 INT_ADCSAT: Gain correction saturation interrupt pending. Bit ...
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Interrupts 12 Interrupts The STM32W108's interrupt system is composed of two parts: a standard ARM® Cortex- M3 Nested Vectored Interrupt Controller (NVIC) that provides top level interrupts, and an Event Manager (EM) that provides second level interrupts. The NVIC and ...
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STM32W108CB, STM32W108HB Table 32. NVIC exception table (continued) Exception NMI Hard Fault Memory Fault Bus Fault Usage Fault - SVCall Debug Monitor - PendSV SysTick Timer 1 Timer 2 Management Baseband Sleep Timer Serial Controller 1 Serial Controller 2 Security ...
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Interrupts The NVIC also contains a software-configurable interrupt prioritization mechanism. The Reset, NMI, and Hard Fault exceptions, in that order, are always the highest priority, and are not software-configurable. All other exceptions can be assigned a 5-bit priority number, with ...
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STM32W108CB, STM32W108HB 12.1.2 Faults Four of the exceptions in the NVIC are faults: Hard Fault, Memory Fault, Bus Fault, and Usage Fault. Of these four, three of the faults (Hard Fault, Memory Fault, and Usage Fault) are all standard ARM® ...
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Interrupts Figure 51. Peripheral interrupts block diagram peripheral interrupt instance OR AND S source interrupt events The description of each peripheral's interrupt configuration and flag registers can be found in the chapters of this datasheet describing each peripheral. Given a ...
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STM32W108CB, STM32W108HB facilitate software detection of such problems. The INT_MISS register is "acknowledged" in the same way as the INT_periphFLAG register-by writing a 1 into the corresponding bit to be cleared. Table 33 provides a map of all peripheral interrupts. ...
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Interrupts 12.3 Nested vectored interrupt controller (NVIC) interrupts 12.3.1 Top-level set interrupts configuration register (INT_CFGSET) Address offset: 0x0100 Reset value INT_IR INT_IR INT_IR INT_IR INT_AD ...
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STM32W108CB, STM32W108HB 12.3.2 Top-level clear interrupts configuration register (INT_CFGCLR) Address offset: 0x0180 Reset value INT_I INT_I INT_I INT_I INT_A RQD RQC RQB RQA Bit ...
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Interrupts INT_I INT_I INT_I INT_I INT_A RQD RQC RQB RQA Bit 16 INT_DEBUG: Write 1 to pend debug interrupt. (Writing 0 has no effect.) Bit 15 INT_IRQD: Write 1 ...
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STM32W108CB, STM32W108HB Bit 13 INT_IRQB: Write 1 to unpend IRQB interrupt. (Writing 0 has no effect.) Bit 12 INT_IRQA: Write 1 to unpend IRQA interrupt. (Writing 0 has no effect.) Bit 11 INT_ADC: Write 1 to unpend ADC interrupt. (Writing ...
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Interrupts Bit 5 INT_SC1: Serial controller 1 interrupt active. Bit 4 INT_SLEEPTMR: Sleep timer interrupt active. Bit 3 INT_BB: Baseband interrupt active. Bit 2 INT_MGMT: Management interrupt active. Bit 1 INT_TIM2: Timer 2 interrupt active. Bit 0 INT_TIM1: Timer 1 ...
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STM32W108CB, STM32W108HB 12.3.7 Auxiliary fault status register (SCS_AFSR) Address offset: 0x0D3C Reset value Bit 3 WRONGSIZE A bus fault resulted from an 8-bit or 16-bit read or write of an ...
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Debug support 13 Debug support The STM32W108 includes a standard Serial Wire and JTAG (SWJ) Interface. The SWJ is the primary debug and programming interface of the STM32W108. The SWJ gives debug tools access to the internal buses of the ...
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STM32W108CB, STM32W108HB 13.1 STM32W108 JTAG TAP connection The STM32W108 MCU integrates two serially-connected JTAG TAPs in the following order; the TMC TAP dedicated for Test (IR is 4-bit wide) and the Cortex™-M3 TAP (IR is 4-bit wide). To access the ...
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Electrical characteristics 14 Electrical characteristics 14.1 Parameter conditions Unless otherwise specified, all voltages are referenced to V 14.1.1 Minimum and maximum values Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply ...
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STM32W108CB, STM32W108HB 14.2 Absolute maximum ratings Stresses above the absolute maximum ratings listed in Table 35: Current permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure ...
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Electrical characteristics 14.3 Operating conditions 14.3.1 General operating conditions Table 37. General operating conditions Symbol – Regulator input voltage (VDD_PADS) Analog and memory input voltage (VDD_24MHZ, – VDD_VCO, VDD_RF, VDD_IF, VDD_PADSA, VDD_MEM, VDD_PRE, and VDD_SYNTH) – Core input voltage (VDD_CORE) ...
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STM32W108CB, STM32W108HB NRST pin A single active low pin, NRST, is provided to reset the system. This pin has a Schmitt triggered input. To afford good noise immunity and resistance to switch bounce, the pin is filtered with the Reset ...
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Electrical characteristics 14.4 ADC characteristics Table 44 describes the key ADC parameters measured at 25°C and VDD_PADS at 3.0 V, for a sampling clock of 1 MHz. ADC_HVSELP and ADC_HVSELN are programmed disable the input buffer. The ...
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STM32W108CB, STM32W108HB Table 45 describes the key ADC parameters measured at 25°C and VDD_PADS at 3.0 V, for a sampling rate of 6 MHz. ADC_HVSELP and ADC_HVSELN are programmed disable the input buffer. The single-ended measurements were ...
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Electrical characteristics Table 46 describes the key ADC parameters measured at 25°C and VDD_PADS at 3.0 V, for a sampling rate of 6 MHz. ADC_HVSELP and ADC_HVSELN are programmed enable the input buffer. The single-ended measurements were ...
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STM32W108CB, STM32W108HB Table 47 lists other specifications for the ADC not covered in Table 46. Table 47. ADC characteristics Parameter VREF VREF output current VREF load capacitance External VREF voltage range External VREF input impedance Minimum input voltage Input buffer ...
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Electrical characteristics 14.5 Clock frequencies 14.5.1 High frequency internal clock characteristics Table 48. High-frequency RC oscillator characteristics Parameter Frequency at reset Frequency Steps Duty cycle Supply dependence Test at supply changes: 1 1.7 V 14.5.2 High frequency external ...
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STM32W108CB, STM32W108HB 14.5.3 Low frequency internal clock characteristics Table 50. Low-frequency RC oscillator characteristics Parameter Nominal Frequency Analog trim step size Supply dependence Frequency dependence 14.5.4 Low frequency external clock characteristics Table 51. Low-frequency crystal oscillator characteristics Parameter Frequency Accuracy ...
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Electrical characteristics 14.6 DC electrical characteristics Table 52. DC electrical characteristics Parameter Regulator input voltage (VDD_PADS) Power supply range (VDD_MEM) Power supply range (VDD_CORE) Deep Sleep Current Quiescent current, internal RC oscillator disabled Quiescent current, including internal RC oscillator Quiescent ...
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STM32W108CB, STM32W108HB Table 52. DC electrical characteristics (continued) Parameter ® ARM Cortex-M3, RAM, and flash memory sleep current ® ARM Cortex-M3, RAM, and flash memory sleep current Serial controller current General purpose timer current General purpose ADC current Rx current ...
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Electrical characteristics Table 52. DC electrical characteristics (continued) Parameter Total Tx current ( = I MAC and baseband, CPU Flash memory ) 196/209 Conditions VDD_PADS = 3 °C; maximum power setting ® (+7 dBm); ARM running at 12 ...
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STM32W108CB, STM32W108HB Figure 55 shows the variation of current in Transmit mode (with the ARM running at 12 MHz). Figure 55. Transmit power consumption Doc ID 16252 Rev 8 Electrical characteristics ® Cortex-M3 197/209 ...
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Electrical characteristics Figure 56 shows typical output power against power setting on the ST reference design. Figure 56. Transmit output power 14.7 Digital I/O specifications Table 53 lists the digital I/O specifications for the STM32W. The digital I/O power (named ...
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STM32W108CB, STM32W108HB Table 53. Digital I/O characteristics (continued) Parameter Output voltage for logic 0 Output voltage for logic 1 Output source current (standard current pad) Output sink current (standard current pad) Output source current high current pad: PA6, PA7, PB6, ...
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Electrical characteristics 14.9 RF electrical characteristics 14.9.1 Receive Table 55 lists the key parameters of the integrated IEEE 802.15.4 receiver on the STM32W. Note: Receive measurements were collected with ST’s STM32W Ceramic Balun Reference Design (Version A0) at 2440 MHz. ...