P87C51FB-4B,557 NXP Semiconductors, P87C51FB-4B,557 Datasheet - Page 34

• Manufacturer Part Number: P87C51FB-4B,557
• Manufacturer: NXP Semiconductors

Philips Semiconductors
(8XC51RX+ ONLY)
HARDWARE WATCHDOG TIMER (ONE-TIME
ENABLED WITH RESET-OUT FOR 89C51RC+/RD+)
The WDT is intended as a recovery method in situations where the
CPU may be subjected to software upset. The WDT consists of a
14-bit counter and the WatchDog Timer reset (WDTRST) SFR. The
WDT is disabled at reset. To enable the WDT, user must write 01EH
and 0E1H in sequence to the WDTRST, SFR location 0A6H. When
WDT is enabled, it will increment every machine cycle while the
oscillator is running and there is no way to disable the WDT except
through reset (either hardware reset or WDT overflow reset). When
WDT overflows, it will drive an output reset HIGH pulse at the
RST-pin.
Using the WDT
To enable the WDT, user must write 01EH and 0E1H in sequence to
the WDTRST, SFR location 0A6H. When WDT is enabled, the user
needs to service it by writing to 01EH and 0E1H to WDTRST to
avoid WDT overflow. The 14-bit counter overflows when it reaches
16383 (3FFFH) and this will reset the device. When using the WDT,
a 1Kohm resistor must be inserted between RST of the device and
the Power On Reset circuitry. When WDT is enabled, it will
increment every machine cycle while the oscillator is running. This
means the user must reset the WDT at least every 16383 machine
cycles. To reset the WDT, the user must write 01EH and 0E1H to
WDTRST. WDTRST is a write only register. The WDT counter
cannot be read or written. When WDT overflows, it will generate an
output RESET pulse at the reset pin. The RESET pulse duration is
98
it should be serviced in those sections of code that will periodically
be executed within the time required to prevent a WDT reset.
2000 Aug 07
80C51 8-bit microcontroller family
8K–64K/256–1K OTP/ROM/ROMless, low voltage (2.7V–5.5V),
low power, high speed (33MHz)
T
OSC
, where T
(RD TO RD+)
OSC
2FF
FF
00
= 1/f
É É É É É
É É É É É
É É É É É
É É É É É
É É É É É
OSC
Figure 28. Internal and External Data Memory Address Space with EXTRAM = 0
256 BYTES
. To make the best use of the WDT,
ERAM
FF
80
00
INTERNAL RAM
INTERNAL RAM
128 BYTES
128 BYTES
LOWER
UPPER
34
FF
80
00
In applications using the Hardware Watchdog Timer of the
P8xC51RD+, a series resistor (1K
between the reset pin and any external components. Without this
resistor the watchdog timer will not function.
FUNCTION
REGISTER
SPECIAL
8XC51RA+/RB+/RC+/RD+/80C51RA+
FFFF
0100
0000
EXTERNAL
8XC51FA/FB/FC/80C51FA
MEMORY
DATA
20%) needs to be included
300 (RD+ only)
SU00834
Product specification
8XC54/58