P87C51FB-4B,557 NXP Semiconductors, P87C51FB-4B,557 Datasheet - Page 39

• Manufacturer Part Number: P87C51FB-4B,557
• Manufacturer: NXP Semiconductors

1. Parameters are valid over operating temperature range unless otherwise specified.
2. Load capacitance for port 0, ALE, and PSEN = 100pF, load capacitance for all other outputs = 80pF.
3. Interfacing the microcontroller to devices with float times up to 45ns is permitted. This limited bus contention will not cause damage to Port 0
4. For frequencies equal or less than 16MHz, see 16MHz “AC Electrical Characteristics”, page 38.
5. Parts are guaranteed to operate down to 0Hz.
Philips Semiconductors
AC ELECTRICAL CHARACTERISTICS
T
NOTES:
2000 Aug 07
amb
t
t
t
t
t
t
t
t
t
t
t
Data Memory
t
t
t
t
t
t
t
t
t
t
t
t
t
t
External Clock
t
t
t
t
Shift Register
t
t
t
t
t
SYMBOL
LHLL
AVLL
LLAX
LLIV
LLPL
PLPH
PLIV
PXIX
PXIZ
AVIV
PLAZ
RLRH
WLWH
RLDV
RHDX
RHDZ
LLDV
AVDV
LLWL
AVWL
QVWX
WHQX
QVWH
RLAZ
WHLH
CHCX
CLCX
CLCH
CHCL
XLXL
QVXH
XHQX
XHDX
XHDV
80C51 8-bit microcontroller family
8K–64K/256–1K OTP/ROM/ROMless, low voltage (2.7V–5.5V),
low power, high speed (33MHz)
drivers.
= 0 C to +70 C or –40 C to +85 C, V
FIGURE
30, 31
30, 31
30, 31
30, 31
30, 31
30, 31
30, 31
30, 31
30, 31
30, 31
30, 31
30, 31
30, 31
29
29
29
29
29
29
29
29
29
29
29
31
33
33
33
33
32
32
32
32
32
ALE pulse width
Address valid to ALE low
Address hold after ALE low
ALE low to valid instruction in
ALE low to PSEN low
PSEN pulse width
PSEN low to valid instruction in
Input instruction hold after PSEN
Input instruction float after PSEN
Address to valid instruction in
PSEN low to address float
RD pulse width
WR pulse width
RD low to valid data in
Data hold after RD
Data float after RD
ALE low to valid data in
Address to valid data in
ALE low to RD or WR low
Address valid to WR low or RD low
Data valid to WR transition
Data hold after WR
Data valid to WR high
RD low to address float
RD or WR high to ALE high
High time
Low time
Rise time
Fall time
Serial port clock cycle time
Output data setup to clock rising edge
Output data hold after clock rising edge
Input data hold after clock rising edge
Clock rising edge to input data valid
CC
PARAMETER
= 5V 10%, V
SS
= 0V
1, 2, 3
39
10t
6t
6t
7t
2t
3t
3t
4t
2t
0.38t
0.38t
t
t
t
t
t
t
CLCL
CLCL
CLCL
CLCL
CLCL
CLCL
CLCL
CLCL
CLCL
12t
CLCL
CLCL
CLCL
CLCL
CLCL
CLCL
MIN
VARIABLE CLOCK
CLCL
0
0
0
CLCL
CLCL
–25
–25
–25
–100
–100
–30
–25
–130
–25
–40
–45
–50
–75
–133
–80
8XC51RA+/RB+/RC+/RD+/80C51RA+
10t
t
t
8t
9t
CLCL
CLCL
4t
3t
5t
5t
2t
3t
t
t
CLCL
CLCL
CLCL
CLCL
CLCL
CLCL
CLCL
CLCL
CLCL
CLCL
CLCL
MAX
10
–t
0
–t
5
5
4
–25
–150
–165
+25
CHCX
CLCX
–65
–60
–80
–90
–28
+50
–133
8XC51FA/FB/FC/80C51FA
33MHz CLOCK
MIN
360
167
21
45
82
82
40
45
80
5
5
0
0
0
5
5
0
Product specification
MAX
105
140
167
55
30
70
10
60
32
90
55
5
0
8XC54/58
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns