DS32508N+ Maxim Integrated Products, DS32508N+ Datasheet - Page 62

• Manufacturer Part Number: DS32508N+
• Description: IC LIU DS3/E3/STS-1 484-BGA
• Manufacturer: Maxim Integrated Products
• Type: Line Interface Units (LIUs)r

Specifications of DS32508N+

• Protocol: IEEE 1149.1
• Voltage - Supply: 1.8V, 3.3V
• Mounting Type: Surface Mount
• Package / Case: 484-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Drivers/receivers: -

9.4 Port Common Registers
Bit 7: Transmit Manual Error Insert (TMEI). When PORT.CR1:MEIMS = 0, this bit is used to insert errors in all
blocks where block-level MEIMS = 1. Error(s) are inserted at the next opportunity after this bit transitions from low
to high. See Section 8.7.5. Note: This bit should be set low immediately after each error insertion.
Bit 6: Transmit Manual Error Insert Mode Select (MEIMS). This bit specifies the source of the error insertion
signal for all block-level error generators that have block-level MEIMS = 1. See Section 8.7.5.
Bit 5: Port Performance Monitor Update Mode (PMUM). This bit specifies the source of the performance
monitoring update signal for all blocks that have block-level PMUM = 1. See Section 8.7.4.
Bit 4: Port Performance Monitor Register Update (PMU). When PORT.CR1:PMUM = 0, this bit is used to
update all of the performance monitor registers where block-level PMUM = 1. When this bit transitions from low to
high, all configured performance monitoring registers are updated with the latest counter values, and all associated
counters are reset. This bit should remain high until the performance monitor update status bit (PORT.SR:PMS)
goes high, and then it should be brought back low, which clears the PMS status bit. If a counter increment occurs
at the exact same time as the counter reset, the counter is loaded with a value of one, and the “counter is non-
zero” latched status bit is set. See Section 8.7.4.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit #
Name
Default
Table 9-4. Port Common Register Map
ADDRESS
OFFSET
0Ch
1Ch
0Ah
0Eh
1Ah
1Eh
00h
02h
04h
06h
08h
10h
12h
14h
16h
18h
0 = Port-level error insertion via PORT.CR1:TMEI
1 = Global error insertion as specified by GLOBAL.CR1:MEIMS
0 = Port-level PM update via PORT.CR1:PMU
1 = Global PM update as specified by GLOBAL.CR1:GPM[1:0]
TMEI
PORT.ISRIE
15
—
PORT.SRIE
REGISTER
PORT.CR1
PORT.CR2
PORT.CR3
0
7
0
PORT.SRL
PORT.INV
PORT.ISR
PORT.SR
—
—
—
—
—
—
—
MEIMS
14
—
0
0
6
Port Control Register 1
Port Control Register 2
Port Control Register 3
Unused
Unused
Port I/O Invert Control Register
Unused
Unused
Port Interrupt Status Register
Unused
Port Interrupt Status Register Interrupt Enable
Unused
Port Status Register
Port Status Register Latched
Port Status Register Interrupt Enable
Unused
PORT.CR1
Port Control Register 1
n * 80h + 00h
PMUM
REGISTER DESCRIPTION
13
—
0
5
0
62 of 130
PMU
12
—
0
4
0
TPD
11
—
0
3
1
RPD
10
—
0
2
1
DS32506/DS32508/DS32512
RSTDP
—
9
0
1
1
RST
—
8
0
0
0