DS32508N+ Maxim Integrated Products, DS32508N+ Datasheet - Page 88

• Manufacturer Part Number: DS32508N+
• Description: IC LIU DS3/E3/STS-1 484-BGA
• Manufacturer: Maxim Integrated Products
• Type: Line Interface Units (LIUs)r

Specifications of DS32508N+

• Protocol: IEEE 1149.1
• Voltage - Supply: 1.8V, 3.3V
• Mounting Type: Surface Mount
• Package / Case: 484-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Drivers/receivers: -

Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit #
Name
Default
Bit 3: Performance Monitoring Update Status (PMS). This bit is set when the performance monitoring registers
(BERT.RBCR
BERT.CR:LPMU bit (BERT.CR:PMUM = 0) or RPMU signal (BERT.CR:PMUM = 1) goes low. See Section 8.7.4.
Bit 1: Bit Error Count (BEC). See Section 8.5.1.
Bit 0: Out of Synchronization (OOS). See Section 8.5.1.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit #
Name
Default
Bit 3: Performance Monitoring Update Status Latched (PMSL). This bit is set when the BERT.SR:PMS bit
transitions from zero to one. When set, this bit causes an interrupt if interrupt enables BERT.SRIE:PMSIE,
PORT.ISRIE:BSRIE and GLOBAL.ISRIE:PnISRIE are all set.
Bit 2: Bit Error Latched (BEL). This bit is set when a bit error is detected in the received pattern. When set, this
bit causes an interrupt if interrupt enables BERT.SRIE:BEIE, PORT.ISRIE:BSRIE and GLOBAL.ISRIE:PnISRIE are
all set.
Bit 1: Bit Error Count Latched (BECL). This bit is set when the BERT.SR:BEC bit transitions from zero to one.
When set, this bit causes an interrupt if interrupt enables BERT.SRIE:BECIE, PORT.ISRIE:BSRIE and
GLOBAL.ISRIE:PnISRIE are all set.
Bit 0: Out of Synchronization Latched (OOSL). This bit is set when the BERT.SR:OOS bit changes state. When
set, this bit causes an interrupt if interrupt enables BERT.SRIE:OOSIE, PORT.ISRIE:BSRIE and
GLOBAL.ISRIE:PnISRIE are all set.
0 = The associated update request signal is low or not all register updates are completed
1 = The requested performance register updates are all completed
0 = the bit error count is zero
1 = the bit error count is one or more
0 = the receive pattern generator is synchronized to the incoming pattern
1 = the receive pattern generator is not synchronized to the incoming pattern
15
15
—
—
—
—
and BERT.RBECR) have been updated. PMS is asynchronously forced low when the
0
7
0
0
7
0
14
14
—
—
—
—
0
6
0
0
6
0
BERT.SR
BERT Status Register
n * 80h + 5Ch
BERT.SRL
BERT Status Register Latched
n * 80h + 5Eh
13
—
—
13
—
—
0
5
0
0
5
0
88 of 130
12
—
—
12
—
—
0
4
0
0
4
0
PMSL
PMS
11
11
—
—
0
3
1
0
3
0
BEL
10
10
—
—
—
0
2
0
0
2
0
DS32506/DS32508/DS32512
BECL
BEC
—
—
9
0
1
0
9
0
1
0
OOSL
OOS
—
—
8
0
0
0
8
0
0
0