CYP15G0101DXB-BBXI Cypress Semiconductor Corp, CYP15G0101DXB-BBXI Datasheet - Page 17

• Manufacturer Part Number: CYP15G0101DXB-BBXI
• Description: IC TXRX HOTLINK 100-LBGA
• Manufacturer: Cypress Semiconductor Corp
• Series: HOTlink II™r
• Type: Transceiverr

Specifications of CYP15G0101DXB-BBXI

• Package / Case: 100-LBGA
• Protocol: Fibre Channel
• Voltage - Supply: 3.135 V ~ 3.465 V
• Mounting Type: Surface Mount
• Product: PHY
• Data Rate: 1500 MBd
• Supply Voltage (max): 3.465 V
• Supply Voltage (min): 3.135 V
• Supply Current: 0.51 A
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Number Of Channels: 1
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: CYP15G0101DX-EVAL - EVAL BRD FOR HOTLINK II
• Number Of Drivers/receivers: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

The local loop-back input (LPEN) allows the serial transmit data
to be routed internally back to the clock and data recovery circuit.
When configured for local loop-back, the transmit serial driver
outputs are forced to output a differential logic-1. This prevents
local diagnostic patterns from being broadcast to attached
remote receivers.
Signal Detect/Link Fault
Each selected line receiver (i.e., that routed to the clock and data
recovery PLL) is simultaneously monitored for
■
■
■
■
All of these conditions must be valid for the signal detect block
to indicate a valid signal is present. This status is presented on
the LFI (link fault indicator) output.
Analog Amplitude
While most signal monitors are based on fixed constants, the
analog amplitude level detection is adjustable to allow operation
with highly attenuated signals, or in high-noise environments.
This adjustment is made through the SDASEL signal, a 3-level
select
of a valid signal at one of three levels, as listed in
The analog signal detect monitor is active for the present line
receiver, as selected by the INSEL input. When configured for
local loop-back (LPEN = HIGH), the analog signal detect monitor
is disabled.
Transition Density
The transition detection logic checks for the absence of any
transitions spanning greater than six transmission characters
(60-bits). If no transitions are present in the data received (within
the referenced period), the transition detection logic asserts LFI.
The LFI output remains asserted until at least one transition is
detected in each of three adjacent received characters.
Table 10. Analog Amplitude Detect Valid Signal Levels
Document Number: 38-02031 Rev. *L
Notes
MID (Open) 280-mV p-p differential
17. REFCLK has no phase or frequency relationship with the recovered clock(s) and only acts as a centering reference to reduce clock synchronization time. REFCLK
18. When REFCLK is configured for half-rate operation (TXRATE
19. The peak amplitudes listed in this table are for typical waveforms that have generally 3–4 transitions for every ten bits. In a worse case environment the signals may
20. When a disabled receive channel is reenabled, the status of the LFI output and data on the parallel outputs may be indeterminate for up to 2 ms.
analog amplitude above limit specified by SDASEL
transition density greater than specified limit
range controller reports the received data stream within normal
frequency range (±1500 ppm)
receive channel enabled.
SDASEL
must be within ±1500 PPM (±0.15%) of the remote transmitter’s PLL reference (REFCLK) frequency. Although transmitting to a HOTLink II receiver necessitates the
frequency difference between the transmitter and receiver reference clocks to be within ±1500-PPM, the stability of the crystal needs to be within the limits specified
by the appropriate standard when transmitting to a remote receiver that is compliant to that standard. For example, to be IEEE 802.3z Gigabit Ethernet compliant,
the frequency stability of the crystal needs to be within ±100 PPM.
REFCLK.
have a sign-wave appearance (highest transition density with repeating 0101...). Signal peak amplitudes levels within this environment type could increase the values
in the table above by approximately 100 mV.
HIGH
LOW
[18]
(ternary) input, which sets the trip point for the detection
140-mV p-p differential
420-mV p-p differential
Typical Signal with Peak Amplitudes
Above
[17]
Table
=
HIGH), this input is sampled (or the outputs change) relative to both the rising and falling edges of
10.
[19]
Range Control
The clock/data recovery (CDR) circuit includes logic to monitor
the frequency of the phase-locked loop (PLL) voltage controlled
oscillator (VCO) used to sample the incoming data stream. This
logic ensures that the VCO operates at, or near the rate of the
incoming data stream for two primary cases:
■
■
To perform this function, the frequency of the VCO is periodically
sampled and compared to the frequency of the REFCLK input. If
the VCO is running at a frequency beyond +1500 ppm
defined by the reference clock frequency, it is periodically forced
to the correct frequency (as defined by REFCLK, SPDSEL, and
TXRATE) and then released in an attempt to lock to the input
data stream. The sampling and relock period of the range control
is calculated as follows: RANGE CONTROL SAMPLING
PERIOD = (REFCLKPERIOD) × (16000).
During the time that the range control forces the PLL VCO to run
at REFCLK × 10 (or REFCLK × 20 when TXRATE = HIGH) rate,
the LFIx output will be asserted LOW. While the PLL is
attempting to re-lock to the incoming data stream, LFIx may be
either HIGH or LOW (depending on other factors such as
transition density and amplitude detection) and the recovered
byte clock (RXCLK) may run at an incorrect rate (depending on
the quality or existence of the input serial data stream). After a
valid serial data stream is applied, it may take up to one RANGE
CONTROL SAMPLING PERIOD before the PLL locks to the
input data stream, after which LFIx should be HIGH.
Receive Channel Enabled
The CYP(V)(W)15G0101DXB receive channel can be enabled
and disabled through the BOE[0] input, as controlled by the
RXLE latch-enable signal. When RXLE = HIGH, the signal
present on the BOE[0] input is passed through the receive
channel enable latch to control the PLL and logic of the receive
channel. The BOE[1:0] input functions are listed in
When RXLE = HIGH and BOE[0] = HIGH, the receive channel is
enabled to receive and recover a serial stream from the line
receiver. When RXLE = HIGH and BOE[0] = LOW, the receive
channel is disabled and internally configured for minimum power
dissipation. When disabled, the channel indicates a constant LFI
output. When RXLE returns LOW, the values present on the
BOE[1:0] inputs are latched in the Receive Channel Enable
Latch, and remain there until RXLE returns HIGH to open the
latch again.
when the incoming data stream resumes after a time in which
it has been “missing.”
when the incoming data stream is outside the acceptable
frequency range.
[20]
CYW15G0101DXB
CYP15G0101DXB
CYV15G0101DXB
Page 17 of 44
Table
8.
[17]
as
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