CYP15G0101DXB-BBXI Cypress Semiconductor Corp, CYP15G0101DXB-BBXI Datasheet - Page 27

• Manufacturer Part Number: CYP15G0101DXB-BBXI
• Description: IC TXRX HOTLINK 100-LBGA
• Manufacturer: Cypress Semiconductor Corp
• Series: HOTlink II™r
• Type: Transceiverr

Specifications of CYP15G0101DXB-BBXI

• Package / Case: 100-LBGA
• Protocol: Fibre Channel
• Voltage - Supply: 3.135 V ~ 3.465 V
• Mounting Type: Surface Mount
• Product: PHY
• Data Rate: 1500 MBd
• Supply Voltage (max): 3.465 V
• Supply Voltage (min): 3.135 V
• Supply Current: 0.51 A
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Number Of Channels: 1
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: CYP15G0101DX-EVAL - EVAL BRD FOR HOTLINK II
• Number Of Drivers/receivers: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

CYP(V)(W)15G0101DXB AC Characteristics
Over the Operating Range
Document Number: 38-02031 Rev. *L
Transmitter LVTTL Switching Characteristics
f
t
t
t
t
t
t
t
f
t
t
t
Receiver LVTTL Switching Characteristics
f
t
t
t
t
t
t
t
t
REFCLK Switching Characteristics Over the Operating Range
f
t
t
t
t
t
t
t
t
Notes
TS
TXCLK
TXCLKH
TXCLKL
TXCLKR
TXCLKF
TXDS
TXDH
TOS
TXCLKO
TXCLKOD+
TXCLKOD–
RS
RXCLKP
RXCLKH
RXCLKL
RXCLKD
RXCLKR
RXCLKF
RXDV–
RXDV+
REF
REFCLK
REFH
REFL
REFD
REFR
REFF
TREFDS
TREFDH
37. This parameter is 154 MHz for CYW15G0101DXB.
38. This parameter is 6.49 ns for CYW15G0101DXB.
39. Tested initially and after any design or process changes that may affect these parameters, but not 100% tested.
40. The ratio of rise time to falling time must not vary by greater than 2:1.
41. For a given operating frequency, neither rise or fall specification can be greater than 20% of the clock-cycle period or the data sheet maximum time.
42. Parallel data output specifications are only valid if all inputs or outputs are loaded with similar DC and AC loads.
43. The duty cycle specification is a simultaneous condition with the t
Parameter
cannot be as large as 30%–70%.
[39, 40, 41]
[43]
[39, 40, 41]
[42]
[42]
[39]
[39]
[39, 40, 41]
[39]
[39, 40, 41]
[39]
TXCLK clock frequency
TXCLK period
TXCLK HIGH time
TXCLK LOW time
TXCLK rise time
TXCLK fall time
Transmit data det-up time toTXCLK (TXCKSEL  LOW)
Transmit data hold time from TXCLK(TXCKSEL  LOW)
TXCLKO clock frequency = 1x or 2x REFCLK frequency
TXCLKO period
TXCLKO+ duty cycle with 60% HIGH time
TXCLKO– duty cycle with 40% HIGH time
RXCLK clock output frequency
RXCLK period
RXCLK HIGH time (RXRATE = LOW)
RXCLK HIGH time (RXRATE = HIGH)
RXCLK LOW time (RXRATE = LOW)
RXCLK LOW time (RXRATE = HIGH)
RXCLK duty cycle centered at 50%
RXCLK rise time
RXCLK fall time
Status and data valid time to RXCLK (RXCKSEL = MID)
Status and data valid time to RXCLK(HALF RATE RECOVERED CLOCK)
Status and data valid time from RXCLK(RXCKSEL = MID)
Status and data valid time from RXCLK(HALF RATE RECOVERED CLOCK)
REFCLK clock frequency
REFCLK period
REFCLK HIGH time (TXRATE = HIGH)
REFCLK HIGH time (TXRATE = LOW)
REFCLK LOW time (TXRATE = HIGH)
REFCLK LOW time (TXRATE = LOW)
REFCLK duty cycle
REFCLK rise time (20% – 80%)
REFCLK fall time (20% – 80%)
Transmit data setup time toREFCLK (TXCKSEL LOW)
Transmit data hold time from REFCLK(TXCKSEL LOW)
Description
REFH
and t
REFL
parameters. This means that at faster character rates the REFCLK duty cycle
5UI – 1.5
5UI – 1.0
5UI – 1.8
5UI – 2.3
2.33
2.33
6.66
6.66
6.66
6.6
2.9
2.9
19.5
19.5
–1.0
–0.5
9.75
5.66
5.66
–1.0
19.5
Min
CYW15G0101DXB
2.2
2.2
0.2
0.2
1.7
0.8
0.3
0.3
5.9
5.9
1.7
0.8
30
CYP15G0101DXB
CYV15G0101DXB
–
–
[38]
[39]
[39]
[38]
[38]
[38]
[39]
[39]
102.56
150
150
150
150
51.28
51.28
26.64
52.28
26.64
52.28
51.28
+0.5
+1.0
+1.0
Max
1.7
1.7
1.2
1.2
70
–
–
–
–
–
–
–
–
–
–
–
–
2
2
–
–
[37]
[37]
[37]
[37]
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MHz
MHz
MHz
MHz
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
%
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