VRS51C1000-40-PG Ramtron, VRS51C1000-40-PG Datasheet - Page 18

• Manufacturer Part Number: VRS51C1000-40-PG
• Description: Microcontrollers (MCU) 64K+1K 40MHz 5V
• Manufacturer: Ramtron

Specifications of VRS51C1000-40-PG

• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 64 KB
• Data Ram Size: 1 KB
• Interface Type: UART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 36
• Number Of Timers: 3
• Operating Supply Voltage: 4.5 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• Package / Case: PDIP-40
• Minimum Operating Temperature: - 40 C
• Lead Free Status / Rohs Status: Details

T
Counting Function
When operating as a counter, the Timer’s register is
incremented at every falling edge of the T0 and T1
signals located at the input of the timer.
When the sampling circuit sees a high immediately
followed by a low in the next machine cycle, the
counter is incremented. Two machine cycles are
required to detect and record an event. In order to be
properly sampled, the duration of the event presented
to the Timer input should be greater than 1/24 of the
oscillator frequency.
Timer 0 / Timer 1 Operating Modes
The user may change the operating mode by setting
the M1 and M0 bits of the TMOD SFR.
Mode 0
A schematic representation of this mode of operation is
presented in the figure below. In Mode 0, the Timer
operates as 13-bit counter made up of 5 LSBs from the
TLx register and the 8 upper bits coming from the THx
register. When an overflow causes the value of the
register to roll over to 0, the TFx interrupt signal goes
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ABLE
5
4
3
2
1
0
Bit
7
6
VRS51C1000
TF1
7
27: T
IMER
TF0
TR0
IE1
IT1
IE0
IT0
Mnemonic
TF1
TR1
TR1
6
0
AND
1 C
TF0
ONTROL
5
Description
Timer 1 Overflow Flag. Set by hardware on
Timer/Counter overflow. Cleared by
hardware on Timer/Counter overflow.
Cleared by hardware when processor
vectors to interrupt routine.
Timer 1 Run Control Bit. Set/cleared by
software to turn Timer/Counter on or off.
Timer 0 Overflow Flag. Set by hardware on
Timer/Counter overflow. Cleared by
hardware when processor vectors to
interrupt routine.
Timer 0 Run Control Bit. Set/cleared by
software to turn Timer/Counter on or off.
Interrupt Edge Flag. Set by hardware when
external interrupt edge is detected. Cleared
when interrupt processed.
Interrupt 1 Type Control Bit. Set/cleared by
software to specify falling edge/low level
triggered external interrupts.
Interrupt 0 Edge Flag. Set by hardware
when external interrupt edge is detected.
Cleared when interrupt processed.
Interrupt 0 Type control bit. Set/cleared by
software to specify falling edge/low level
triggered external interrupts.
R
EGISTER
TR0
4
(TCON) –SFR 88
IE1
3
IT1
2
H
IE0
1
IT0
0
to 1. The count value is validated as soon as TRx goes
to 1 and the GATE bit is 0, or when INTx is 1.
F
Mode 1
Mode 1 is almost identical to Mode 0, with the
difference being that in Mode 1, the counter/timer uses
the full 16-bits of the Timer.
Mode 2
In this Mode, the register of the Timer is configured as
an 8-bit auto-re-loadable Counter/Timer. In Mode 2,
the TLx is used as the counter. In the event of a
counter overflow, the TFx flag is set to 1 and the value
contained in THx, which is preset by software, is
reloaded into the TLx counter. The value of THx
remains unchanged.
F
IGURE
IGURE
T1 / T0 Pin
INT1 / INT0 pin
TR1/TR0
TR1 / TR0
GATE1 / GATE0
GATE1 /
T1/T0 pin
GATE0
INT1 /
INT0 pin
Fosc
Fosc
10: T
11: T
IMER
IMER
/C
/C
OUNTER
OUNTER
÷12
÷12
1 M
1 M
ODE
ODE
0
1
0
1
C/T1 / C/T0 =0
C/T1 / CT0 =1
0: 13-B
2: 8-
C/T1 / C/T0 = 1
C/T1 / C/T0 = 1
BIT
IT
Control
A
C
UTOMATIC
Control
OUNTER
page 18 of 48
R
CLK
ELOAD
0
0
0
TH1 / TH0
0
TL1 / TL0
Mode 0
Mode 1
TF1 /
TF0
TF1 / TF0
TH1 / TH0
TL1 / TL0
4
7
7
7
7
INT
INT
Reload