VRS51C1000-40-PG Ramtron, VRS51C1000-40-PG Datasheet - Page 7

• Manufacturer Part Number: VRS51C1000-40-PG
• Description: Microcontrollers (MCU) 64K+1K 40MHz 5V
• Manufacturer: Ramtron

Specifications of VRS51C1000-40-PG

• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 64 KB
• Data Ram Size: 1 KB
• Interface Type: UART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 36
• Number Of Timers: 3
• Operating Supply Voltage: 4.5 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• Package / Case: PDIP-40
• Minimum Operating Temperature: - 40 C
• Lead Free Status / Rohs Status: Details

VRS51C1000 ISPVx Firmware boot program
An ISP boot loader program is available for the
VRS51C1000 (ISPVx Firmware, x = revision, see
Ramtron website for latest revision).
The ISPVx Firmware enables In-System-Programming
of the VRS51C1000 on the final application PCB using
the device’s UART interface. See the following figure
for a hardware configuration example.
configurations are also possible.
F
See Ramtron’s website in order to download the
“Versa Ware ISP” Window’s™ application which allows
communication with the ISPVx firmware.
The VRS51C1000 can be ordered with or without the
ISPVx bootloader firmware (see Ordering information
section of this Datasheet for part number information).
The
programmed into the VRS51C1000 by the user.
Source code is included with the Versa Ware ISP
application software.
For more information on the ISPVx firmware, please
consult the “VRS51C1000 ISPVx Firmware User
Guide.pdf” available on the Ramtron web site.
VRS51C1000 IAP feature
The VRS51C1000 IAP feature refers to the ability of
the processor to self-program the Flash memory from
within the user program.
Five SFR registers serve to control the IAP operation.
The description of these registers is provided below.
______________________________________________________________________________________________
www.ramtron.com
To PC
IGURE
VRS51C1000
4: VRS51C1000 I
ISPVx
150k
bootloader
NTERFACE FOR
PNP
I
N
-S
YSTEM
firmware
Creset
Rreset
P
ROGRAMMING
can
VRS51C1000
TXD
RXD
RES
(with ISPV2
Firmware)
also
Other
be
System Control Register
By default upon reset, the IAP feature of the
VRS51C1000 is de-activated. The IAPE bit of the
SYSCON register is used to enable (and disable) the
VRS51C1000 IAP function.
T
IAP Flash Address and Data Registers
The IAPFADHI and IAPADLO registers are used to
specify the address at which the IAP function will be
performed.
T
T
The IAPFDATA SFR register contains the Data byte
required to perform the IAP function.
T
IAP Flash Control Register
The VRS51C1000 IAP function operation is controlled
by the IAP Flash Control register, IAPFCTRL.
Setting the IAPSTART bit to 1, starts the execution of
the IAP command specified by the IAPFCT[1:0] bits of
the IAP Flash Control register.
ABLE
ABLE
ABLE
ABLE
WDR
Bit
7
6
5
4
3
2
1
0
7
7
7
7
6: S
7:IAP F
8:IAP F
9:IAP F
YSTEM
Mnemonic
WDR
Unused
Unused
Unused
Unused
IAPE
XRAME
ALEI
6
LASH
LASH
LASH
6
6
6
C
ONTROL
D
A
A
DDRESS
DDRESS
ATA
5
Unused
5
5
5
R
R
EGISTER
EGISTER
H
L
Description
This is the Watchdog Timer reset bit. It will
be set to 1 when the reset signal generated
by WDT overflows.
-
-
-
-
IAP function enable bit
768 byte on-chip enable bit
ALE output inhibit bit, which is used to
reduce EMI.
OW
IGH
IAPFADLO[15:8]
IAPFADHI[15:8]
IAPFDATA[7:0]
4
4
4
4
- SFR F5
- SFR F4
- SFR F6
(SYSCON) – SFR BF
3
H
H
3
3
3
H
IAPE
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2
2
2
2
H
XRAME
1
1
1
1
ALEI
0
0
0
0