SFPA8192Q1BO2TO-I-QT-223-STD Swissbit NA Inc, SFPA8192Q1BO2TO-I-QT-223-STD Datasheet - Page 18

• Manufacturer Part Number: SFPA8192Q1BO2TO-I-QT-223-STD
• Description: FLASH SSD SMART UDMA 2.5" 8GB
• Manufacturer: Swissbit NA Inc
• Series: P-120r

Specifications of SFPA8192Q1BO2TO-I-QT-223-STD

• Memory Size: 8GB
• Memory Type: FLASH
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 1052-1025

Table 23: Ultra DMA Data Burst Timing Descriptions
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Notes:
Swissbit AG
Industriestrasse 4
CH-9552 Bronschhofen
Switzerland
2CYCTYP
CYC
2CYC
DS
DH
DVS
DVH
CS
CH
CVS
CVH
ZFS
DZFS
FS
LI
MLI
UI
AZ
ZAH
ZAD
ENV
RFS
RP
IORDYZ
ZIORDY
ACK
SS
Name Comment
1.
2. 80-conductor cabling shall be required in order to meet setup (t
3. Timing for t
4. For all modes the parameter t
5. The parameters t
Typical sustained average two cycle time
Cycle time allowing for asymmetry and clock variations (from STROBE edge to STROBE edge)
Two cycle time allowing for clock variations (from rising edge to next rising edge or from
falling edge to next falling edge of STROBE)
Data setup time at recipient (from data valid until STROBE edge)
Data hold time at recipient (from STROBE edge until data may become invalid)
Data valid setup time at sender (from data valid until STROBE edge)
Data valid hold time at sender (from STROBE edge until data may become invalid)
CRC word setup time at device
CRC word hold time device
CRC word valid setup time at host (from CRC valid until -DMACK negation)
CRC word valid hold time at sender (from -DMACK negation until CRC may become invalid)
Time from STROBE output released-to-driving until the first transition of critical timing.
Time from data output released-to-driving until the first transition of critical timing.
First STROBE time (for device to first negate DSTROBE from STOP during a data in burst)
Limited interlock time
Interlock time with minimum
Unlimited interlock time
Maximum time allowed for output drivers to release (from asserted or negated)
Minimum delay time required for output
drivers to assert or negate (from released)
Envelope time (from -DMACK to STOP and -HDMARDY during data in burst initiation and
from DMACK to STOP during data out burst initiation)
Ready-to-final-STROBE time (no STROBE edges shall be sent this long after negation of
-DMARDY)
Ready-to-pause time (that recipient shall wait to pause after negating -DMARDY)
Maximum time before releasing IORDY
Minimum time before driving IORDY
Setup and hold times for -DMACK (before assertion or negation)
Time from STROBE edge to negation of DMARQ or assertion of STOP (when sender terminates
a burst)
The parameters t
Ultra DMA Data-In Burst Host Termination Timing), and t
to-sender interlocks, i.e., one agent (either sender or recipient) is waiting for the other agent to
respond with a signal before proceeding. t
value. t
defined maximum.
modes greater than 2.
connector where the Data and STROBE signals have the same capacitive load value. Due to
reflections on the cable, these timing measurements are not valid in a normally functioning
system.
up on IORDY- giving it a known state when released.
configuration with a single device located at the end of the cable. This could result in the minimum
values for t
MLI
is a limited time-out that has a defined minimum. t
DS
DVS
Swissbit reserves the right to change products or specifications without notice.
and t
, t
DVH
UI
DS
, t
, t
, and t
DH
MLI
CVS
for mode 5 at the middle connector being 3.0 and 3.9 ns respectively.
and t
(in Figure 6: Ultra DMA Data-In Burst Device Termination Timing and Figure 7:
DH
for mode 5 are defined for a recipient at the end of the cable only in a
CVH
ZIORDY
shall be met for lumped capacitive loads of 15 and 40 pF at the
may be greater than t
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UI
is an unlimited interlock that has no maximum time
LI
ENV
indicate sender-to-recipient or recipient-
due to the fact that the host has a pull-
LI
is a limited time-out that has a
DS
, t
CS
P-120_data_sheet_PA-QxBO_Rev100.doc
) and hold (t
DH
, t
CH
) times in
Notes
2, 5
2, 5
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