SFPA8192Q1BO2TO-I-QT-223-STD Swissbit NA Inc, SFPA8192Q1BO2TO-I-QT-223-STD Datasheet - Page 19

• Manufacturer Part Number: SFPA8192Q1BO2TO-I-QT-223-STD
• Description: FLASH SSD SMART UDMA 2.5" 8GB
• Manufacturer: Swissbit NA Inc
• Series: P-120r

Specifications of SFPA8192Q1BO2TO-I-QT-223-STD

• Memory Size: 8GB
• Memory Type: FLASH
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 1052-1025

Table 24: Ultra DMA Sender and Recipient IC Timing Requirements
Notes:
Table 25: Ultra DMA AC Signal Requirements
Note:
6.3.2.4.1 Initiating an Ultra DMA Data-In Burst
Swissbit AG
Industriestrasse 4
CH-9552 Bronschhofen
Switzerland
1.
2.
3.
1.
a) An Ultra DMA Data-In burst is initiated by following the steps lettered below. The timing diagram is
b) The following steps shall occur in the order they are listed unless otherwise specifically allowed:
c)
d) The device shall assert DMARQ to initiate an Ultra DMA burst. After assertion of DMARQ the device
e) Steps (c), (d), and (e) may occur in any order or at the same time. The host shall assert STOP.
f)
g) The host shall negate -CS0, -CS1, DA2, DA1, and DA0. The host shall keep -CS0, -CS1, DA2, DA1, and
h) Steps (c), (d), and (e) shall have occurred at least t
i)
Name
Name
t
t
S
S
t
t
DVSIC
DVHIC
DSIC
DHIC
RISE
FALL
All timing measurement switching points(low to high and high to low) shall be taken at 1.5 V.
The correct data value shall be captured by the recipient given input data with a slew rate of 0.4 V/ns rising and
falling and the input STROBE with a slew rate of 0.4 V/ns rising and falling at t
through 1.5 V).
The parameters t
signals have the same capacitive load value. Noise that may couple onto the output signals from external
sources has not been included in these values.
The sender shall be tested while driving an 18 inch long, 80 conductor cable with PVC insulation material. The
signal under test shall be cut at a test point so that it has not trace, cable or recipient loading after the test
point. All other signals should remain connected through to the recipient. The test point may be located at any
point between the sender’s series termination resistor and one half inch or less of conductor exiting the
connector. If the test point is on a cable conductor rather than the PCB, an adjacent ground conductor shall
also be cut within one half inch of the connector.
The test load and test points should then be soldered directly to the exposed source side connectors. The test
loads consist of a 15 pF or a 40 pF, 5%, 0.08 inch by 0.05 inch surface mount or smaller size capacitor from the
test point to ground. Slew rates shall be met for both capacitor values.
Measurements shall be taken at the test point using a <1 pF, >100 kOhm, 1 GHz or faster probe and a 500 MHz
or faster oscilloscope. The average rate shall be measured from 20% to 80% of the settled VOH level with data
transitions at least 120 ns apart. The settled VOH level shall be measured as the average output high level
under the defined testing conditions from 100 nsec after 80% of a rising edge until 20% of the subsequent
falling edge.
shown in Figure 3: Ultra DMA Data-In Burst Initiation Timing. The associated timing parameters are
specified in Table 22: Ultra DMA Data Burst Timing Requirements and are described in Table 23: Ultra
DMA Data Burst Timing Descriptions.
The host shall keep -DMACK in the negated state before an Ultra DMA burst is initiated.
shall not negate DMARQ until after the first negation of DSTROBE.
The host shall negate -HDMARDY.
DA0 negated until after negating -DMACK at the end of the burst.
keep -DMACK asserted until the end of an Ultra DMA burst.
The host shall release D[15:00] within t
Comments
Recipient IC data setup time (from
data valid until STROBE edge)
(see note 2)
Recipient IC data hold time (from
STROBE edge until data may
become invalid) (see note 2)
Sender IC data valid setup time
(from data valid until STROBE
edge) (see note 3)
Sender IC data valid hold time
(from STROBE edge until data
may become invalid) (see note 3)
Comment
Rising Edge Slew Rate for any signal
Falling Edge Slew Rate for any signal
Swissbit reserves the right to change products or specifications without notice.
DVSIC
and t
DVHIC
shall be met for lumped capacitive loads of 15 and 40 pF at the IC where all
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www.swissbit.com
AZ
14.7
72.9
Min Max Min Max Min Max Min Max Min Max
4.8
9.0
Mode 0
after asserting -DMACK.
UDMA
(ns)
[V/ns]
ACK
50.9
Min
9.7
4.8
9.0
Mode 1
before the host asserts -DMACK. The host shall
UDMA
(ns)
33.9
6.8
4.8
9.0
Mode 2
UDMA
(ns)
[V/ns]
P-120_data_sheet_PA-QxBO_Rev100.doc
Max
1.25
1.25
DSIC
and t
22.6
6.8
4.8
9.0
Mode 3
UDMA
DHIC
(ns)
timing (as measured
Notes
4.8
4.8
9.5
9.0
1
1
Page
Mode4
UDMA
Revision: 1.00
(ns)
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