SFPA8192Q1BO2TO-I-QT-223-STD Swissbit NA Inc, SFPA8192Q1BO2TO-I-QT-223-STD Datasheet - Page 23

• Manufacturer Part Number: SFPA8192Q1BO2TO-I-QT-223-STD
• Description: FLASH SSD SMART UDMA 2.5" 8GB
• Manufacturer: Swissbit NA Inc
• Series: P-120r

Specifications of SFPA8192Q1BO2TO-I-QT-223-STD

• Memory Size: 8GB
• Memory Type: FLASH
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 1052-1025

Figure 6: Ultra DMA Data-In Burst Device Termination Timing
Notes: The definitions for the STOP, HDMARDY, and DSTROBE signal lines are no longer in effect after DMARQ
and DMACK are negated.
6.3.2.4.5 Host Terminating an Ultra DMA Data-In Burst
The host terminates an Ultra DMA Data-In burst by following the steps lettered below. The timing
diagram is shown in Figure 7: Ultra DMA Data-In Burst Host Termination Timing. The timing
parameters are specified in Table 22: Ultra DMA Data Burst Timing Requirements and are
described in Table 23: Ultra DMA Data Burst Timing Descriptions.
The following steps shall occur in the order they are listed unless otherwise specifically allowed:
Swissbit AG
Industriestrasse 4
CH-9552 Bronschhofen
Switzerland
a) The host shall not initiate Ultra DMA burst termination until at least one data word of an Ultra DMA
b) The host shall initiate Ultra DMA burst termination by negating -HDMARDY. The host shall continue
c)
d) If the host negates -HDMARDY within t
e) The host shall assert STOP no sooner than t
f)
g) If DSTROBE is negated, the device shall assert DSTROBE within t
h) The device shall release D[15:00] no later than t
i)
burst has been transferred.
to negate -HDMARDY until the Ultra DMA burst is terminated.
The device shall stop generating DSTROBE edges within t
host shall be prepared to receive zero or one additional data words. If the host negates
HDMARDYgreater than t
prepared to receive zero, one or two additional data words. The additional data words are a result
of cable round trip delay and t
STOP again until after the Ultra DMA burst is terminated.
The device shall negate DMARQ within t
DMARQ again until after the Ultra DMA burst is terminated.
data shall be transferred during this assertion. The host shall ignore this transition on DSTROBE.
DSTROBE shall remain asserted until the Ultra DMA burst is terminated.
The host shall drive DD D[15:00] no sooner than t
step, the host may first drive D[15:00] with the result of its CRC calculation (see 6.3.2.5 ).
Swissbit reserves the right to change products or specifications without notice.
SR
after the device has generated a DSTROBE edge, then the host shall be
RFS
timing for the device.
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SR
LI
after the device has generated a DSTROBE edge, then the
after the host has asserted STOP. The device shall not assert
RP
after negating -HDMARDY. The host shall not negate
AZ
ZAH
after negating DMARQ.
after the device has negated DMARQ. For this
RFS
of the host negating -HDMARDY
LI
after the host has asserted STOP. No
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