ADV7195KS Analog Devices Inc, ADV7195KS Datasheet - Page 28

• Manufacturer Part Number: ADV7195KS
• Description: IC DAC VID-HDTV 3CH-11BIT 52MQFP
• Manufacturer: Analog Devices Inc
• Type: Video Encoderr

Specifications of ADV7195KS

• Rohs Status: RoHS non-compliant
• Applications: HDTV, MPEG, Image Processing
• Voltage - Supply, Analog: 3.3V
• Voltage - Supply, Digital: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 52-MQFP, 52-PQFP
• Adc/dac Resolution: 11b
• Screening Level: Commercial
• Package Type: MQFP
• Pin Count: 52
• For Use With: EVAL-ADV7195EB - BOARD EVAL FOR ADV7195
• Lead Free Status / RoHS Status: Not Compliant

ADV7195
MODE REGISTER 2
MR1 (MR27–MR20)
(Address (SR4–SR0) = 02H)
Figure 53 shows the various operations under the control of
Mode Register 2.
MR2 BIT DESCRIPTION
Y Delay (MR20–MR22)
With these bits it is possible to delay the Y signal with respect to
the falling edge of the horizontal sync signal by up to four pixel
clock cycles. Figure 52 demonstrates this facility.
Color Delay (MR23–MR25)
With these bits it is possible to delay the color signals with
respect to the falling edge of the horizontal sync signal by up to
four pixel clock cycles. Figure 52 demonstrates this facility.
Reserved (MR26–MR27)
A “0” must be written to these bits.
PrPb DELAY
Y DELAY
NO DELAY
NO DELAY
DELAY
MAX
MAX DELAY
ZERO MUST BE
TO THESE BITS
A ZERO MUST
WRITTEN TO
MR37–MR36
THESE BITS
BE WRITTEN
MR27–MR26
MR37
MR27
MR36
MR26
MR35
0
1
DAC C CONTROL
Y OUTPUT
POWER-DOWN
NORMAL
PrPb OUTPUT
MR35
MR25
MR25 MR24 MR23
0
0
0
0
1
MR34
DAC B CONTROL
0
1
COLOR DELAY
0
0
1
1
0
POWER-DOWN
NORMAL
MR34
MR24
0
1
0
1
0
MR33
0
1
DAC A CONTROL
0 PCLK
1 PCLK
2 PCLK
3 PCLK
4 PCLK
MODE REGISTER 3
MR3 (MR37–MR30)
(Address (SR4-SR0) = 03H)
Figure 54 shows the various operations under the control of
Mode Register 3.
MR3 BIT DESCRIPTION
HDTV Enable (MR30)
When this bit is set to “1,” the ADV7195 reverts to HDTV
mode. When set to “0” the ADV7195 reverts to Progressive
Scan Mode (PS mode).
Reserved (MR31–MR32)
A “0” must be written to these bits.
DAC A Control (MR33)
Setting this bit to “1” enables DAC A, otherwise this DAC is
powered down.
DAC B Control (MR34)
Setting this bit to “1” enables DAC B, otherwise this DAC is
powered down.
DAC C Control (MR35)
Setting this bit to “1” enables DAC C, otherwise this DAC is
powered down.
Reserved (MR36–MR37)
A “0” must be written to these bits.
POWER-DOWN
NORMAL
MR33
MR23
ZERO MUST BE
WRITTEN TO
MR32–MR31
THESE BITS
MR32
MR22
MR22 MR21 MR20
0
0
0
0
1
0
0
1
1
0
Y DELAY
MR31
MR21
MR30
0
1
0
1
0
HDTV ENABLE
0
1
DISABLE
ENABLE
0 PCLK
1 PCLK
2 PCLK
3 PCLK
4 PCLK
MR30
MR20