SAA7115HL/V1,518 NXP Semiconductors, SAA7115HL/V1,518 Datasheet - Page 442
SAA7115HL/V1,518
Manufacturer Part Number
SAA7115HL/V1,518
Description
IC DIGITAL VIDEO DECODER 100LQFP
Manufacturer
NXP Semiconductors
Type
Video Decoderr
Specifications of SAA7115HL/V1,518
Package / Case
100-LQFP
Applications
Set-Top Boxes
Mounting Type
Surface Mount
Mounting Style
SMD/SMT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Voltage - Supply, Analog
-
Voltage - Supply, Digital
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
935270666518
SAA7115HLBE-T
SAA7115HLBE-T
SAA7115HLBE-T
SAA7115HLBE-T
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
SAA7115HL/V1,518
Manufacturer:
Sigma Designs Inc
Quantity:
10 000
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Philips Semiconductors
prefetch
pseudo-op for prefd(0)
SYNTAX
[ IF rguard ] pref rsrc1
FUNCTION
DESCRIPTION
(Note: pseudo operations cannot be used in assembly files.)
cache_block_mask) and stores the data into the data cache. This operation is not guaranteed to be executed. The
prefetch unit will not execute this operation when the data to be prefetched is already in the data cache. A pref
operation will not be executed when the cache is already occupied with 2 cache misses, when the operation is issued.
of the prefetch operation. If the LSB of rguard is 1, prefetch operation is executed; otherwise, it is not executed.
NOTE: This operation may only be supported in TM-1000, TM-1100, TM-1300 and
PNX1300/01/02/11. It is not guaranteed to be available in future generations of Trimedia
products.
r10 = 0xabcd,
cache_block_size = 0x40
r10 = 0xabcd, r11 = 0,
cache_block_size = 0x40
r10 = 0xabff, r11 = 1,
cache_block_size = 0x40
The pref operation is a pseudo operation transformed by the scheduler into an prefd(0) with the same arguments.
The pref operation loads the one full cache block size of memory value from the address computed by ((rsrc1+0) &
The pref operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the execution
EXAMPLES
if rguard then {
}
cache_block_mask = ~(cache_block_size - 1)
data_cache <- mem[(rsrc1 + 0) & cache_block_mask]
Initial Values
pref r10
IF r11 pref r10
IF r11 pref r10
Operation
PRELIMINARY SPECIFICATION
Loads a cache line for the address space from
0xabc0 to 0x0xabff from the main memory. If the data
is already in the cache, the operation is not executed.
since guard is false, pref operation is not executed
Loads a cache line for the address space from
0xabc0 to 0x0xabff from the main memory. If the data
is already in the cache, the operation is not executed.
PNX1300/01/02/11 DSPCPU Operations
prefr allocd allocr allocx
Function unit
Operation code
Number of operands
Modifier
Modifier range
Latency
Issue slots
pref16x pref32x prefd
Result
ATTRIBUTES
SEE ALSO
dmemspec
209
pref
1
5
-
-
-
A-144
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