PCA9557D,112 NXP Semiconductors, PCA9557D,112 Datasheet

IC I/O EXPANDER I2C 8B 16SOIC

PCA9557D,112

Manufacturer Part Number
PCA9557D,112
Description
IC I/O EXPANDER I2C 8B 16SOIC
Manufacturer
NXP Semiconductors
Datasheet

Specifications of PCA9557D,112

Package / Case
16-SOIC (3.9mm Width)
Interface
I²C, SMBus
Number Of I /o
8
Interrupt Output
No
Frequency - Clock
400kHz
Voltage - Supply
2.3 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Includes
POR
Logic Family
PCA9557
Number Of Lines (input / Output)
8.0 / 8.0
Operating Supply Voltage
2.3 V to 5.5 V
Power Dissipation
200 mW
Operating Temperature Range
- 40 C to + 85 C
Input Voltage
5 V
Logic Type
I2C, SMBus
Maximum Clock Frequency
400 KHz
Mounting Style
SMD/SMT
Number Of Input Lines
8.0
Number Of Output Lines
8.0
Output Current
50 mA
Output Voltage
5 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
568-1060-5
935270674112
PCA9557D
1. General description
2. Features
The PCA9557 is a silicon CMOS circuit which provides parallel input/output expansion for
SMBus and I
8-bit output port register, and an I
and a high-impedance open-drain output pin, IO0.
The system master can enable the PCA9557’s I/O as either input or output by writing to
the configuration register. The system master can also invert the PCA9557 inputs by
writing to the active HIGH polarity inversion register. Finally, the system master can reset
the PCA9557 in the event of a time-out by asserting a LOW in the reset input.
The power-on reset puts the registers in their default state and initializes the
I
occur without de-powering the part.
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
2
C-bus/SMBus state machine. The RESET pin causes the same reset/initialization to
PCA9557
8-bit I
Rev. 06 — 11 June 2008
Lower voltage, higher performance migration path for the PCA9556
8 general purpose input/output expander/collector
Input/output configuration register
Active HIGH polarity inversion register
I
Internal power-on reset
Noise filter on SCL/SDA inputs
Active LOW reset input
3 address pins allowing up to 8 devices on the I
High-impedance open-drain on IO0
No glitch on power-up
Power-up with all channels configured as inputs
Low standby current
Operating power supply voltage range of 2.3 V to 5.5 V
5 V tolerant inputs/outputs
0 kHz to 400 kHz clock frequency
ESD protection exceeds 2000 V HBM per JESD22-A114, 150 V MM per
JESD22-A115 and 1000 V CDM per JESD22-C101
Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA
Three packages offered: SO16, TSSOP16, HVQFN16
2
C-bus and SMBus interface logic
2
C-bus and SMBus I/O port with reset
2
C-bus applications. The PCA9557 consists of an 8-bit input port register,
2
C-bus/SMBus interface. It has low current consumption
2
C-bus/SMBus
Product data sheet

Related parts for PCA9557D,112

PCA9557D,112 Summary of contents

Page 1

PCA9557 8-bit I Rev. 06 — 11 June 2008 1. General description The PCA9557 is a silicon CMOS circuit which provides parallel input/output expansion for SMBus and I 8-bit output port register, and an I and a high-impedance open-drain output ...

Page 2

... NXP Semiconductors 3. Ordering information Table 1. Type number PCA9557D PCA9557PW PCA9557BS 3.1 Ordering options Table 2. Type number PCA9557D PCA9557PW PCA9557BS 4. Block diagram SCL SDA V V RESET Fig 1. PCA9557 Product data sheet Ordering information Package Name Description SO16 plastic small outline package; 16 leads; ...

Page 3

... NXP Semiconductors shift register shift register write configuration write pulse read pulse shift register write polarity Fig 2. PCA9557 Product data sheet data from configuration register data from pulse FF CK output port register data from pulse On power-up or reset, all registers return to default values. ...

Page 4

... NXP Semiconductors shift register shift register write configuration write pulse read pulse shift register write polarity Fig 3. PCA9557 Product data sheet data from configuration register data from pulse FF CK output port register data from pulse On power-up or reset, all registers return to default values. ...

Page 5

... NXP Semiconductors 5. Pinning information 5.1 Pinning SCL SDA Fig 4. Fig 6. 5.2 Pin description Table 3. Symbol SCL SDA IO0 IO1 PCA9557 Product data sheet RESET IO7 IO6 PCA9557D IO5 IO0 6 11 IO4 IO1 7 10 IO3 IO2 SS 002aad272 Pin configuration for SO16 ...

Page 6

... NXP Semiconductors Table 3. Symbol V SS IO2 IO3 IO4 IO5 IO6 IO7 RESET V DD [1] HVQFN16 package die supply ground is connected to both the V V pin must be connected to the supply ground for proper device operation. For enhanced thermal, SS electrical, and board-level performance, the exposed pad needs to be soldered to the board using a corresponding thermal pad on the board, and for proper heat conduction through the board thermal vias need to be incorporated in the PCB in the thermal pad region ...

Page 7

... NXP Semiconductors 7. Functional description Refer to 7.1 Device address Following a START condition the bus master must output the address of the slave it is accessing. The address of the PCA9557 is shown in internal pull-up resistors are incorporated on the hardware selectable address pins and they must be pulled HIGH or LOW. ...

Page 8

... NXP Semiconductors 7.3 Register descriptions 7.3.1 Register 0 - Input port register This register is a read-only port. It reflects the incoming logic levels of the pins, regardless of whether the pin is defined as an input or an output by the Configuration register. Writes to this register have no effect. ...

Page 9

... NXP Semiconductors 7.4 Power-on reset When power is applied reset condition until V and the PCA9557 registers and I states. Thereafter, V 7.5 RESET input A reset can be accomplished by holding the RESET pin LOW for a minimum of t PCA9557 registers and SMBus/I until the RESET input is once again HIGH. This input requires a pull-up resistor active connection is used ...

Page 10

... NXP Semiconductors SDA SCL Fig 11. Definition of START and STOP conditions 8.2 System configuration A device generating a message is a ‘transmitter’; a device receiving is the ‘receiver’. The device that controls the message is the ‘master’ and the devices which are controlled by the master are the ‘ ...

Page 11

... NXP Semiconductors Fig 13. Acknowledgement on the I 8.4 Bus transactions Data is transmitted to the PCA9557 registers using Write Byte transfers (see and Figure transfers (see SCL slave address SDA START condition write to port data out from port Fig 14. Write to output port register SCL slave address ...

Page 12

... NXP Semiconductors slave address SDA START condition acknowledge slave address (cont (repeated) START condition Fig 16. Read from register slave address SDA START condition read from port data into DATA 1 port Remark: This figure assumes the command byte has previously been programmed with 00h. ...

Page 13

... NXP Semiconductors 9. Application design-in information 1 MASTER CONTROLLER SCL SDA RESET V SS Device address configured as 0011 100x for this example. IO0, IO2, IO3 configured as outputs. IO1, IO4, IO5 configured as inputs. IO6, IO7 are not used. Fig 18. Typical application 9.1 Minimizing I ...

Page 14

... NXP Semiconductors Fig 19. High value resistor in parallel with 10. Limiting values Table 9. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter V supply voltage DD V input voltage I I input current I I maximum allowed input current IHL(max) through protection diode (IO1 to IO7) ...

Page 15

... NXP Semiconductors 11. Static characteristics Table 10. Static characteristics Symbol Parameter Supplies V supply voltage DD I supply current DD I LOW-level standby current stbL I HIGH-level standby current stbH I additional standby current stb V power-on reset voltage POR Input SCL; input/output SDA V LOW-level input voltage IL V HIGH-level input voltage ...

Page 16

... NXP Semiconductors 12. Dynamic characteristics Table 11. Dynamic characteristics Symbol Parameter f SCL clock frequency SCL t bus free time between a STOP and BUF START condition t hold time (repeated) START condition HD;STA t set-up time for a repeated START SU;STA condition t set-up time for STOP condition SU;STO ...

Page 17

... NXP Semiconductors SDA t BUF t LOW SCL t HD;STA P S Fig 21. Definition of timing on the I START SCL SDA RESET 50 % IOn Fig 22. Definition of RESET timing PCA9557 Product data sheet HD;DAT HIGH SU;DAT 2 C-bus rec(rst) Rev. 06 — 11 June 2008 PCA9557 2 8-bit I C-bus and SMBus I/O port with reset ...

Page 18

... NXP Semiconductors 13. Package outline SO16: plastic small outline package; 16 leads; body width 3 pin 1 index 1 DIMENSIONS (inch dimensions are derived from the original mm dimensions) A UNIT max. 0.25 1.45 mm 1.75 0.25 0.10 1.25 0.010 0.057 inches 0.069 0.01 0.004 0.049 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. ...

Page 19

... NXP Semiconductors TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4 pin 1 index 1 DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 0.95 mm 1.1 0.25 0.05 0.80 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. ...

Page 20

... NXP Semiconductors HVQFN16: plastic thermal enhanced very thin quad flat package; no leads; 16 terminals; body 0.85 mm terminal 1 index area terminal 1 index area DIMENSIONS (mm are the original dimensions) (1) A UNIT max. 0.05 0. 0.2 0.00 0.23 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. ...

Page 21

... NXP Semiconductors 14. Handling information Inputs and outputs are protected against electrostatic discharge in normal handling. However completely safe you must take normal precautions appropriate to handling integrated circuits. 15. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “ ...

Page 22

... NXP Semiconductors • Process issues, such as application of adhesive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave • Solder bath specifications, including temperature and impurities 15.4 Reflow soldering Key characteristics in reflow soldering are: • ...

Page 23

... NXP Semiconductors Fig 26. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description” . 16. Abbreviations Table 14. Acronym CBT CDM CMOS ESD HBM 2 I C-bus I/O LED MM PCB POR ...

Page 24

... NXP Semiconductors 17. Revision history Table 15. Revision history Document ID Release date PCA9557_6 20080611 • Modifications: Section 2 • Table 11 “Dynamic “4 ns” to “6 ns” (for both Standard-mode and Fast-mode) • Updated soldering information PCA9557_5 20070912 PCA9557_4 20041124 (9397 750 13336) PCA9557_3 20021213 ...

Page 25

... Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...

Page 26

... NXP Semiconductors 20. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 3.1 Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 2 4 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 2 5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 5 5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 6 System diagram . . . . . . . . . . . . . . . . . . . . . . . . . 6 7 Functional description . . . . . . . . . . . . . . . . . . . 7 7.1 Device address . . . . . . . . . . . . . . . . . . . . . . . . . 7 7.2 Control register . . . . . . . . . . . . . . . . . . . . . . . . . 7 7.3 Register descriptions . . . . . . . . . . . . . . . . . . . . 8 7.3.1 Register 0 - Input port register . . . . . . . . . . . . . 8 7 ...

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