PCA9574PW,118 NXP Semiconductors, PCA9574PW,118 Datasheet
PCA9574PW,118
Specifications of PCA9574PW,118
PCA9574PW-T
PCA9574PW-T
Related parts for PCA9574PW,118
PCA9574PW,118 Summary of contents
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PCA9574 8-bit I with reset and interrupt Rev. 02 — 27 July 2009 1. General description The PCA9574 is a CMOS device that provides 8 bits of General Purpose parallel Input/Output (GPIO) expansion in low voltage processor and handheld battery ...
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... NXP Semiconductors The PCA9574 is available in TSSOP16, HVQFN16 and HXQFN16U packages and is specified over the +85 C industrial temperature range. 2. Features I 400 kHz I I Compliant with I I Separate supply rails for core logic and I/O bank provides voltage level shifting I 1 3.6 V operation with level shifting feature I Very low standby current: < ...
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... NXP Semiconductors I Gaming machines I Instrumentation and test measurement 4. Ordering information Table 1. Type number Package PCA9574PW PCA9574BS PCA9574HR 4.1 Ordering options Table 2. Type number PCA9574PW PCA9574BS PCA9574HR 5. Block diagram A0 SCL SDA V DD RESET V SS Fig 1. PCA9574_2 Product data sheet 2 8-bit I C-bus and SMBus, level translating, low voltage GPIO ...
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... NXP Semiconductors data from shift register configuration register data from D Q shift register FF write configuration CK Q pulse write pulse read pulse BUS-HOLD AND PULL-UP/PULL-DOWN CONTROL data from shift register write polarity pulse Fig 2. Simplified schematic of the I/Os (P0 to P7) PCA9574_2 Product data sheet ...
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... NXP Semiconductors 6. Pinning information 6.1 Pinning INT A0 RESET Fig 3. Fig 5. PCA9574_2 Product data sheet 2 8-bit I C-bus and SMBus, level translating, low voltage GPIO SDA 3 14 SCL PCA9574PW DD(IO) 002aad052 Pin configuration for TSSOP16 PCA9574HR terminal 1 index area Transparent top view Pin confi ...
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... NXP Semiconductors 6.2 Pin description Table 3. Symbol INT A0 RESET DD(IO SCL SDA V DD [1] HVQFN16, HXQFN16U package die supply ground is connected to both V V pin must be connected to supply ground for proper device operation. For enhanced thermal, electrical, SS and board level performance, the exposed pad needs to be soldered to the board using a corresponding thermal pad on the board and for proper heat conduction through the board, thermal vias need to be incorporated in the PCB in the thermal pad region ...
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... NXP Semiconductors 7.2 Command register Following the successful acknowledgement of the slave address + R/W bit, the bus master will send a byte to the PCA9574, which will be stored in the Command register. Fig 7. The lowest 3 bits are used as a pointer to determine which register will be accessed. Only a command register code with the 3 least signifi ...
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... NXP Semiconductors 7.5 Reading the port registers In order to read data from the PCA9574, the bus master must first send the PCA9574 address with the least significant bit set to a logic 0 (see command byte is sent after the address and determines which register will be accessed. ...
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... NXP Semiconductors 7.5.3 Register 2 - Bus-hold/pull-up/pull-down enable register Bit 0 of this register allows the user to enable/disable the bus-hold feature for the I/O pins. Setting the bit 0 to logic 1 enables bus-hold feature for the I/O bank. In this mode, the pull-up/pull-downs will be disabled. Setting the bit 0 to logic 0 disables bus-hold feature. ...
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... NXP Semiconductors 7.5.4 Register 3 - Pull-up/pull-down selector register When bus-hold feature is not selected and bit 1 of Register 2 is set to logic 1, the I/O port can be configured to have pull-up or pull-down by programming the pull-up/pull-down register. Setting a bit to logic 1 will select a 100 k pull-up resistor for that I/O pin. Setting a bit to logic 0 will select a 100 k pull-down resistor for that I/O pin ...
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... NXP Semiconductors 7.5.6 Register 5 - Output port register This register is an output-only port. It reflects the outgoing logic levels of the pins defined as outputs by Register 4. Bit values in this register have no effect on pins defined as inputs. In turn, reads from this register reflect the value that is in the flip-flop controlling the output selection, not the actual pin value ...
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... NXP Semiconductors 7.5.8 Register 7 - Interrupt status register This register is read-only used to identify the source of interrupt. Remark: If the interrupts are masked, this register will return all zeros. Table 12. Legend: * default value. Bit 7.6 Power-on reset When power is applied reset condition until V and the PCA9574 registers and state machine will initialize to their default states. The ...
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... NXP Semiconductors 5. Once the right byte has been sent and correctly acknowledged, the master sends a STOP command to end the Software Reset sequence: the PCA9574 then resets to the default value (power-up value) and is ready to be addressed again within the specified bus free time. If the master sends a Repeated START instead, no reset is performed. The I (at any time ‘ ...
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... NXP Semiconductors 8.1.1 START and STOP conditions Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line while the clock is HIGH is defined as the START condition (S). A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP condition (P) (see Fig 9 ...
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... NXP Semiconductors 8.3 Acknowledge The number of data bytes transferred between the START and the STOP conditions from transmitter to receiver is not limited. Each byte of eight bits is followed by one acknowledge bit. The acknowledge bit is a HIGH level put on the bus by the transmitter, whereas the master generates an extra acknowledge related clock pulse. ...
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... NXP Semiconductors 9. Bus transactions Data is transmitted to the PCA9574 registers using ‘Write Byte’ transfers (see and Figure Data is read from the PCA9574 registers using ‘Read Byte’ transfers (see Figure 15). SCL slave address SDA START condition write to port data out from port Fig 12 ...
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... NXP Semiconductors slave address SDA START condition acknowledge from slave slave address (cont (repeated) START condition Fig 14. Read from register data into port INT t v(INT) SCL slave address SDA START condition read from port This figure assumes the command byte has previously been programmed with 00h. ...
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... NXP Semiconductors 10. Application design-in information MASTER CONTROLLER SCL SDA INT RESET V SS Device address configured as 0100 0000b for this example. P0, P2, P3 configured as outputs. P1, P4, P5 configured as inputs. P6, P7 are not used and must be configured as outputs. Fig 16. Typical application 11 ...
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... NXP Semiconductors 12. Static characteristics Table 14. Static characteristics DD(IO) Symbol Parameter Supplies V supply voltage DD V input/output supply voltage DD(IO) I supply current DD I LOW-level standby current stbL I HIGH-level standby current Standby mode; V stbH V power-on reset voltage POR Input SCL; input/output SDA ...
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... NXP Semiconductors 3 (V) 2.0 1 Fig 17 3 DD(IO) PCA9574_2 Product data sheet 2 8-bit I C-bus and SMBus, level translating, low voltage GPIO 002aae765 4 (V) 3.0 2.0 1 100 amb = 1 Fig 18 Rev. 02 — 27 July 2009 PCA9574 002aae766 amb 3 3 DD(IO) © NXP B.V. 2009. All rights reserved. ...
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... NXP Semiconductors 13. Dynamic characteristics Table 15. Dynamic characteristics DD(IO) Symbol Parameter f SCL clock frequency SCL t bus free time between a STOP and BUF START condition t hold time (repeated) START condition HD;STA t set-up time for a repeated START SU;STA condition t set-up time for STOP condition SU ...
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... NXP Semiconductors SDA t BUF t LOW SCL t HD;STA P S Fig 19. Definition of timing START SCL SDA RESET rec(rst Fig 20. Reset timing PCA9574_2 Product data sheet 2 8-bit I C-bus and SMBus, level translating, low voltage GPIO HD;DAT HIGH SU;DAT 30 % Rev. 02 — 27 July 2009 PCA9574 ...
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... NXP Semiconductors 14. Test information R = load resistance load capacitance includes jig and probe capacitance termination resistance should be equal to the output impedance Z T (1) For SDA, no 500 pull-down. Fig 21. Test circuitry for switching times PCA9574_2 Product data sheet 2 8-bit I C-bus and SMBus, level translating, low voltage GPIO ...
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... NXP Semiconductors 15. Package outline TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4 pin 1 index 1 DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 0.95 mm 1.1 0.25 0.05 0.80 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. ...
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... NXP Semiconductors HVQFN16: plastic thermal enhanced very thin quad flat package; no leads; 16 terminals; body 0.85 mm terminal 1 index area terminal 1 index area DIMENSIONS (mm are the original dimensions) (1) A UNIT max. 0.05 0. 0.2 0.00 0.18 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. ...
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... NXP Semiconductors HXQFN16U: plastic thermal enhanced extremely thin quad flat package; no leads; 16 terminals; UTLP based; body 0.5 mm terminal 1 index area terminal 1 index area 16 DIMENSIONS (mm are the original dimensions) A UNIT max 0.05 0.25 2.1 mm 0.5 0.00 0.15 1.9 OUTLINE VERSION IEC SOT1046 Fig 24 ...
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... NXP Semiconductors 16. Handling information All input and output pins are protected against ElectroStatic Discharge (ESD) under normal handling. When handling ensure that the appropriate precautions are taken as described in JESD625-A or equivalent standards. 17. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “ ...
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... NXP Semiconductors • Process issues, such as application of adhesive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave • Solder bath specifications, including temperature and impurities 17.4 Reflow soldering Key characteristics in reflow soldering are: • ...
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... NXP Semiconductors Fig 25. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description” . 18. Abbreviations Table 18. Acronym CBT CDM CMOS DUT ESD GPIO HBM I C-bus IC LED LP MM PCB ...
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... NXP Semiconductors 19. Revision history Table 19. Revision history Document ID Release date PCA9574_2 20090727 • Modifications: Added HXQFN16U package option (type number PCA9574HR; SOT1046-1) • Section 2 th – 4 bullet item: deleted phrase “and 3.6 V tolerant” th – 7 bullet item: 1 “Totem pole source and 3 mA sink” ...
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... Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...
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... NXP Semiconductors 22. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 4 Ordering information . . . . . . . . . . . . . . . . . . . . . 3 4.1 Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 3 5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 5 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6 7 Functional description . . . . . . . . . . . . . . . . . . . 6 7.1 Device address . . . . . . . . . . . . . . . . . . . . . . . . . 6 7.2 Command register . . . . . . . . . . . . . . . . . . . . . . 7 7.3 Register definitions . . . . . . . . . . . . . . . . . . . . . . 7 7.4 Writing to port registers . . . . . . . . . . . . . . . . . . 7 7 ...