AMIS49587C5871RG ON Semiconductor, AMIS49587C5871RG Datasheet - Page 19

IC MODEM PLC 50/60MHZ 28PLCC

AMIS49587C5871RG

Manufacturer Part Number
AMIS49587C5871RG
Description
IC MODEM PLC 50/60MHZ 28PLCC
Manufacturer
ON Semiconductor
Datasheets

Specifications of AMIS49587C5871RG

Baud Rates
Selectable
Interface
SCI
Voltage - Supply
3 V ~ 3.6 V
Mounting Type
Surface Mount
Package / Case
28-PLCC
Number Of Transmitters
1
Power Supply Requirement
Single
Package Type
PLCC
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
28
Operating Temperature (max)
70C
Dual Supply Voltage (typ)
Not RequiredV
Dual Supply Voltage (max)
Not RequiredV
Dual Supply Voltage (min)
Not RequiredV
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Data Format
-
Lead Free Status / Rohs Status
Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AMIS49587C5871RG
Manufacturer:
ON
Quantity:
3 400
Part Number:
AMIS49587C5871RG
Manufacturer:
ON Semiconductor
Quantity:
10 000
input is lower than the falling threshold level and a logic one
when the input is higher than the rising threshold level. The
6.1.2 50/60 Hz PLL
for a PLL. The PLL generates the clock CHIP_CLK which
is 8 times the bit rate and which is in phase with the rising
edge crossings. The PLL locks on the zero crossing from
negative to positive phase. The bit rate is always an even
multiple of the mains frequency, so following combinations
are possible:
The zero crossing detector output is logic zero when the
The output of the zero crossing detector is used as an input
MAINS
FROM
1 M Ω
ZeroCross
VIR
VIF
Figure 13. Zero Cross Detector Signals and Timing (Example for 50 Hz)
V
M50HZIN
M50HZIN
MAINS
3V3_A
Figure 12. Zero Cross Detector with Falling Edge Debouncer
M50Hz_IN
t
ZCD
http://onsemi.com
10 ms
19
falling edges of the output of the zero crossing detector are
de- -bounced by a period between 0.5 ms and 1 ms. The
Rising edges are not de- -bounced.
internal timers in order to maintain the CHIP_CLK timing.
Table 22. CHIP_CLK IN FUNCTION OF SELECTED
BAUD RATE AND MAINS FREQUENCY
In case no zero crossings are detected the PLL freezes its
BAUD[1:0]
Debounce
00
01
10
11
00
01
10
11
Filter
t
MAINS_FREQ
DEBOUNCE
ZeroCross
50 Hz
60 Hz
t
Clock & Control
= 0,5 .. 1 ms
PLL
CHIP_CLK
Baudrate
1200
2400
1440
2880
300
600
360
720
CHIP_CLK
19200 Hz
23040 Hz
11520Hz
2400 Hz
4800 Hz
2880 Hz
5760 Hz
9600Hz

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