MT46H8M16LFBF-6 IT:KTR Micron Technology Inc, MT46H8M16LFBF-6 IT:KTR Datasheet - Page 70
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MT46H8M16LFBF-6 IT:KTR
Manufacturer Part Number
MT46H8M16LFBF-6 IT:KTR
Description
Manufacturer
Micron Technology Inc
Type
DDR SDRAMr
Datasheet
1.MT46H8M16LFBF-6_ITKTR.pdf
(94 pages)
Specifications of MT46H8M16LFBF-6 IT:KTR
Organization
8Mx16
Density
128Mb
Address Bus
15b
Access Time (max)
6.5/5ns
Maximum Clock Rate
166MHz
Operating Supply Voltage (typ)
1.8V
Package Type
VFBGA
Operating Temp Range
-40C to 85C
Operating Supply Voltage (max)
1.95V
Operating Supply Voltage (min)
1.7V
Supply Current
80mA
Pin Count
60
Mounting
Surface Mount
Operating Temperature Classification
Industrial
Lead Free Status / Rohs Status
Compliant
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Figure 32: Data Input Timing
PDF: 09005aef8331b3e9
128mb_mobile_ddr_sdram_t35m.pdf - Rev. F 03/10 EN
Notes:
Data for any WRITE burst can be truncated by a subsequent PRECHARGE command, as
shown in Figure 42 (page 79) and Figure 43 (page 80). Note that only the data-in
pairs that are registered prior to the
any subsequent data-in should be masked with DM, as shown in Figure 42 (page 79)
and Figure 43 (page 80). After the PRECHARGE command, a subsequent command to
the same bank cannot be issued until
DQS
DM
CK#
DQ
CK
1. WRITE command issued at T0.
2.
3.
4. For x16, LDQS controls the lower byte; UDQS controls the upper byte. For x32, DQS0 con-
5. For x16, LDM controls the lower byte; UDM controls the upper byte. For x32, DM0 con-
4
5
t
t
trols DQ[7:0], DQS1 controls DQ[15:8], DQS2 controls DQ[23:16], and DQS3 controls
DQ[31:24].
trols DQ[7:0], DM1 controls DQ[15:8], DM2 controls DQ[23:16], and DM3 controls
DQ[31:24].
DSH (MIN) generally occurs during
DSS (MIN) generally occurs during
t
WPRES
T0
t
1
DQSS
t DS
T1
D
IN
t
WPRE
t
DSH
t DH
70
T1n
2
t
Transitioning Data
t
DQSL
DSS
128Mb: x16, x32 Mobile LPDDR SDRAM
t
WR period are written to the internal array, and
3
t
T2
t
RP is met.
t
DQSS (MAX).
DQSS (MIN).
Micron Technology, Inc. reserves the right to change products or specifications without notice.
t
t
DQSH
DSH
T2n
2
t
t
WPST
DSS
3
T3
Don’t Care
© 2007 Micron Technology, Inc. All rights reserved.
WRITE Operation
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