AD9891KBC Analog Devices Inc, AD9891KBC Datasheet - Page 36

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AD9891KBC

Manufacturer Part Number
AD9891KBC
Description
IC CCD SIGNAL PROC/GEN 64-CSPBGA
Manufacturer
Analog Devices Inc
Type
CCD Signal Processor, 10-Bitr
Datasheet

Specifications of AD9891KBC

Rohs Status
RoHS non-compliant
Input Type
Logic
Output Type
Logic
Interface
3-Wire Serial
Mounting Type
Surface Mount
Package / Case
64-CSPBGA
Analog Front End Type
CCD
Analog Front End Category
Video
Interface Type
Serial (3-Wire)
Operating Supply Voltage (min)
2.7/3V
Resolution
10b
Number Of Adc's
1
Power Supply Type
Analog/Digital
Operating Temp Range
-20C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
64
Package Type
CSPBGA
Number Of Channels
1
Current - Supply
-
Lead Free Status / RoHS Status
Not Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AD9891KBC
Manufacturer:
AD
Quantity:
55
Part Number:
AD9891KBC
Manufacturer:
ADI
Quantity:
329
AD9891/AD9895
I/O Block
AFE
Timing Core
CLO
Oscillator
V1
V2
V3
V4
VSG1
VSG2
VSG3
VSG4
VSG5
VSG6
VSG7
VSG8
SUBCK
VSUB
MSHUT
STROBE
H1
H2
H3
H4
RG
LD/FD
CLPOB/
PBLK
VD
HD
DCLK
CLO
DOUT
NOTES
1
2
3
4
First column represents the defaults when OUT_CONT==LO (OUT_CONT takes precedence). Power-Down 1, 2, and 3 are direct decodes of the OPR MODE
Power-Down 2 will set H[1,2,3,4]DRV and RGDRV to 3’h1 (3.5 mA). Power -Down 3 will three-state the H and RG clocks (set H[1,2,3,4]DRV and RGDRV to 3’h0).
Both the Timing Core and the CLO Oscillator will be powered down in Power-Down 3.
To exit Power-Down 3, first write a 2’b00 to OPRMODE[1:0] (will wake up the oscillator and the timing core), then reset the timing core after ~500 µs to guarantee lock.
Register Bits [1:0]. These polarities assume OUT_CONT==HI.
OUT_CONT== LOW
ON
ON
ON
LOW
LOW
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
LOW
LOW
LOW
LOW
HIGH
LOW
HIGH
LOW
LOW
HIGH
vdhdpol
vdhdpol
LOW
running
LOW
1
Table XVI. Power-Down Mode Operation
Power-Down 1
OFF
ON
ON
LOW
LOW
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
LOW
LOW
LOW
LOW
HIGH
LOW
HIGH
LOW
LOW
HIGH
running
running
running
running
LOW
–36–
1
Power-Down 2
OFF
OFF
ON
LOW
LOW
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
HIGH
LOW
LOW
LOW
LOW (3.5 mA)
HIGH (3.5 mA)
LOW (3.5 mA)
HIGH (3.5 mA)
LOW (3.5 mA)
LOW
HIGH
vdhdpol
vdhdpol
LOW
running
LOW
1, 2
Power-Down 3
OFF
OFF
OFF
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
LOW
LOW
LOW
LOW
LOW
HIGH
LOW
1, 3, 4
REV. A

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