AD9891KBC Analog Devices Inc, AD9891KBC Datasheet - Page 43

• Manufacturer Part Number: AD9891KBC
• Description: IC CCD SIGNAL PROC/GEN 64-CSPBGA
• Manufacturer: Analog Devices Inc
• Type: CCD Signal Processor, 10-Bitr

Specifications of AD9891KBC

• Rohs Status: RoHS non-compliant
• Input Type: Logic
• Output Type: Logic
• Interface: 3-Wire Serial
• Mounting Type: Surface Mount
• Package / Case: 64-CSPBGA
• Analog Front End Type: CCD
• Analog Front End Category: Video
• Interface Type: Serial (3-Wire)
• Operating Supply Voltage (min): 2.7/3V
• Resolution: 10b
• Number Of Adc's: 1
• Power Supply Type: Analog/Digital
• Operating Temp Range: -20C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 64
• Package Type: CSPBGA
• Number Of Channels: 1
• Current - Supply: -
• Lead Free Status / RoHS Status: Not Compliant

Address
00
01
02
03
04
05
06
07
08
09
0A
Address
010
017
018
019
01A
01B
01C
01D
01E
01F
020
021
022
023
024
025
026
027
028
029
02A
02B
031
032
033
REV. A
Content
[5:0]
[1:0]
[5:0]
[3:0]
[5:0]
[1:0]
[5:0]
[5:0]
[5:0]
[5:0]
[5:0]
Content
[5:0]
[0]
[0]
[5:0]
[5:0]
[0]
[0]
[5:0]
[0]
[0]
[0]
[0]
[0]
[0]
[0]
[0]
[0]
[0]
[0]
[0]
[0]
[5:0]
[0]
[1:0]
[0]
Bit
Width
6
2
6
4
6
2
6
6
6
6
6
Bit
Width
6
1
1
6
6
1
1
6
1
1
1
1
1
1
1
1
1
1
1
1
1
6
1
2
1
Table XX. MISCELLANEOUS/EXTRA Register Map
Default
Value
10
00
05
01
00
02
00
00
00
00
00
Default
Value
00
00
00
00
00
00
00
00
00
00
00
01
00
00
00
00
00
00
00
00
00
00
01
02
01
Table XIX. AFE Register Map
Register Name
OPRMODE[5:0]
OPRMODE[7:6]
CCDGAIN[5:0]
CCDGAIN[9:6]
REFBLACK[5:0]
REFBLACK[7:6]
CTLMODE
PXGA GAIN0
PXGA GAIN1
PXGA GAIN2
PXGA GAIN3
Register Name
INTIAL2
SW_RESET
OUT_CONT
UPDATE[5:0]
UPDATE[11:6]
PREVENTUPDATE
READBACK
DOUTPHASE
DCLKMODE
CLIDIVIDE
DISABLERESTORE
FIELDVAL
H1HBLKRETIME
H3HBLKRETIME
SYNCENABLE
SYNCPOL
SYNCSUSPEND
OUTPUTLD
OUTPUTPBLK
TGCORE_RSTB
FTRANCCD
INTIAL1
SINGLE_CLAMP
DOUT_DELAY
OSC_PWRDOWN
–43–
See Power-Up Sequence. Should be set to “4.”
Serial Data Update Control. Sets the line (HD)
Prevents the Update of the VD Updated Registers
Re-time H1/H2 HBLK to Internal H1 Clock
Re-time H3/H4 HBLK to Internal H3 Clock
TG Core Reset_bar (0 = Hold TG Core in Reset,
CLPDM = CLPOB when Set to 1 (Only CLPOB
Delay from DCLK to DOUT (0 = No Delay,
CLO Oscillator Power-Down (0 = Oscillator Is
Register Description
Software Reset (1 = Reset All Registers to Default)
Output Control (0 = Make All Outputs DC Inactive)
within the field for the serial data update to occur.
Serial Interface Readback Enable
DOUT Phase Control
DCLK Mode (0 = DCLK Tracks DOUT Phase,
1 = DCLK Is CLO, i.e., CLI Inverse)
Divide CLI Input Clock by 2
Disable CCDIN DC Restore Circuit during PBLK
(1 = Disable)
Reset Internal Field Pulse Value (0 = Next Field
Odd, 1 = Next Field Even)
External Synchronization Enable (1 = Enable)
SYNC Active Polarity (0 = Active LOW)
Suspend Clocks during SYNC Active (1 = Suspend)
Assign LD/FD Output (0 = FD, 1 = LD)
Assign CLPOB/PBLK Output (0 = CLPOB,
1 = PBLK)
1 = Resume Operation)
Frame Transfer CCD Mode (1 = VSG1–VSG4
Become V5–V8 Out)
See Power-Up Sequence. Should be set to “53.”
Registers Used).
1 = 4 ns, 2 = 8 ns, 3 = 12 ns)
Powered Down)
AFE Operation Mode (See Table XXXI.)
Control Mode (See Table XXXI.)
Register Description
VGA Gain (Defaults to 2 dB)
Black Clamp Level
PxGA Color 0 Gain
PxGA Color 1 Gain
PxGA Color 2 Gain
PxGA Color 3 Gain
AD9891/AD9895