DS92LV2411SQX/NOPB National Semiconductor, DS92LV2411SQX/NOPB Datasheet - Page 37

• Manufacturer Part Number: DS92LV2411SQX/NOPB
• Description: IC SERIALIZER 24BIT 48LLP
• Manufacturer: National Semiconductor

Specifications of DS92LV2411SQX/NOPB

• Function: Serializer
• Data Rate: 1.2Gbps
• Input Type: LVCMOS
• Output Type: CML
• Number Of Inputs: 24
• Number Of Outputs: 1
• Voltage - Supply: 1.71 V ~ 1.89 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-LLP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Power Up Requirements and PDB Pin
The VDD (V
1.5 ms with a monotonic rise. If slower then 1.5 ms then a
capacitor on the PDB pin is needed to ensure PDB arrives
after all the VDD have settled to the recommended operating
voltage. When PDB pin is pulled to V
to use a 10 kΩ pull-up and a 22 uF cap to GND to delay the
PDB input signal.
TRANSMISSION MEDIA
The Ser/Des chip set is intended to be used in a point-to-point
configuration, through a PCB trace, through twisted pair cable
or through 50Ω coaxial cables. The Ser and Des provide in-
ternal terminations providing a clean signaling environment.
The interconnect for the differential serial interface should
present a differential impedance of 100Ω. Use cables and
connectors that have matched differential impedance to min-
imize impedance discontinuities. Shielded or un-shielded ca-
bles may be used depending upon the noise environment and
application requirements.
For 50Ω coaxial cable serial interfaces, any unused input or
output pin must be terminated with an 0.1 µF AC coupling
capacitor and a 50Ω resistor to ground. The PCB traces and
serial interconnect should have a single ended impedance of
50Ω.
LIVE LINK INSERTION
The Ser and Des devices support live pluggable applications.
The automatic receiver lock to random data “plug & go” hot
insertion capability allows the DS92LV2412 to attain lock to
the active data stream during a live insertion event.
PCB LAYOUT AND POWER SYSTEM CONSIDERATIONS
Circuit board layout and stack-up for the Ser/Des devices
should be designed to provide low-noise power feed to the
device. Good layout practice will also separate high frequency
or high-level inputs and outputs to minimize unwanted stray
noise pickup, feedback and interference. Power system per-
formance may be greatly improved by using thin dielectrics (2
to 4 mils) for power / ground sandwiches. This arrangement
provides plane capacitance for the PCB power system with
low-inductance parasitics, which has proven especially effec-
tive at high frequencies, and makes the value and placement
of external bypass capacitors less critical. External bypass
capacitors should include both RF ceramic and tantalum elec-
trolytic types. RF capacitors may use values in the range of
0.01 uF to 0.1 uF. Tantalum capacitors may be in the 2.2 uF
to 10 uF range. Voltage rating of the tantalum capacitors
should be at least 5X the power supply voltage being used.
Surface mount capacitors are recommended due to their
smaller parasitics. When using multiple capacitors per supply
pin, locate the smaller value closer to the pin. A large bulk
capacitor is recommend at the point of power entry. This is
typically in the 50uF to 100uF range and will smooth low fre-
DDn
and V
DDIO
) supply ramp should be faster than
DDIO
, it is recommended
37
quency switching noise. It is recommended to connect power
and ground pins directly to the power and ground planes with
bypass capacitors connected to the plane with via on both
ends of the capacitor. Connecting power or ground pins to an
external bypass capacitor will increase the inductance of the
path.
A small body size X7R chip capacitor, such as 0603, is rec-
ommended for external bypass. Its small body size reduces
the parasitic inductance of the capacitor. The user must pay
attention to the resonance frequency of these external bypass
capacitors, usually in the range of 20-30 MHz. To provide ef-
fective bypassing, multiple capacitors are often used to
achieve low impedance between the supply rails over the fre-
quency of interest. At high frequency, it is also a common
practice to use two vias from power and ground pins to the
planes, reducing the impedance at high frequency.
Some devices provide separate power and ground pins for
different portions of the circuit. This is done to isolate switch-
ing noise effects between different sections of the circuit.
Separate planes on the PCB are typically not required. Pin
Description tables typically provide guidance on which circuit
blocks are connected to which power pin pairs. In some cas-
es, an external filter many be used to provide clean power to
sensitive circuits such as PLLs.
Use at least a four layer board with a power and ground plane.
Locate LVCMOS signals away from the CML lines to prevent
coupling from the LVCMOS lines to the CML lines. Closely-
coupled differential lines of 100 Ohms are typically recom-
mended for differential interconnect. The closely coupled
lines help to ensure that coupled noise will appear as com-
mon-mode and thus is rejected by the receivers. The tightly
coupled lines will also radiate less.
Information on the LLP style package is provided in National
Application Note: AN-1187.
SERIAL INTERCONNECT GUIDELINES
See AN-1108 and AN-905 for full details.
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Additional general guidance can be found in the LVDS
Owner’s Manual - available in PDF format from the National
web site at: www.national.com/lvds
Use 100Ω coupled differential pairs
Use the S/2S/3S rule in spacings
– S = space between the pair
– 2S = space between pairs
– 3S = space to LVCMOS signal
Minimize the number of Vias
Use differential connectors when operating above
500Mbps line speed
Maintain balance of the traces
Minimize skew within the pair
Terminate as close to the TX outputs and RX inputs as
possible
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