DS92LV2411SQX/NOPB National Semiconductor, DS92LV2411SQX/NOPB Datasheet
DS92LV2411SQX/NOPB
Specifications of DS92LV2411SQX/NOPB
Available stocks
Related parts for DS92LV2411SQX/NOPB
DS92LV2411SQX/NOPB Summary of contents
Page 1
... DS92LV2412 is offered in a 60-pin LLP package. Both de- vices operate over the full industrial temperature range of -40° +85°C. Applications Diagram TRI-STATE ® registered trademark of National Semiconductor Corporation. © 2011 National Semiconductor Corporation DS92LV2411/DS92LV2412 Features ■ 24–bit data, 3–bit control, 5 – 50 MHz clock ■ ...
Page 2
Block Diagrams Ordering Information NSID Package Description DS92LV2411SQE 48–pin LLP, 7.0 X 7.0 X 0.8 mm, 0.5 mm pitch DS92LV2411SQ 48–pin LLP, 7.0 X 7.0 X 0.8 mm, 0.5 mm pitch DS92LV2411SQX 48–pin LLP, 7.0 X 7.0 X 0.8 mm, ...
Page 3
DS92LV2411 Pin Diagram Serializer - DS92LV2411 — Top View 3 30065319 www.national.com ...
Page 4
DS92LV2411 Serializer Pin Descriptions Pin Name Pin # I/O, Type LVCMOS Parallel Interface DI[7:0] 34, 33, 32, 29, I, LVCMOS 28, 27, 26 pull-down DI[15:8] 42, 41, 40, 39, I, LVCMOS 38, 37, 36 pull-down DI[23:16] ...
Page 5
Pin Name Pin # I/O, Type CONFIG 13 LVCMOS [1:0] w/ pull-down ID[ Analog SCL 8 I, LVCMOS Open Drain SDA 9 I/O, LVCMOS Open Drain BISTEN 31 I, LVCMOS w/ pull-down RES[2:0] 18, 16, 15 ...
Page 6
DS92LV2412 Pin Diagram www.national.com Deserializer - DS92LV2412 — Top View 6 30065320 ...
Page 7
DS92LV2412 Deserializer Pin Descriptions Pin Name Pin # I/O, Type LVCMOS Parallel Interface DO[7:0] 33, 34, 35, I, STRAP, 36, 37, 39, O, LVCMOS 40, 41 DO[15:8] 20, 21, 22, I, STRAP, 23, 25, 26, O, LVCMOS 27, 28 DO[23:16] ...
Page 8
Pin Name Pin # I/O, Type Control and Configuration — STRAP PINS For a High State, use a 10 kΩ pull power-up and set device configuration. Pin Number listed along with shared data output name in square ...
Page 9
Pin Name Pin # I/O, Type Control and Configuration PDB 59 I, LVCMOS w/ pull-down ID[ Analog SCL 3 I, LVCMOS Open Drain SDA 2 I/O, LVCMOS Open Drain BISTEN 44 I, LVCMOS w/ pull-down RES 47 I, ...
Page 10
... Absolute Maximum Ratings If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage – V (1.8V) DDn Supply Voltage – V DDIO LVCMOS I/O Voltage −0.3V to (VDDIO + 0.3V) Receiver Input Voltage Driver Output Voltage ...
Page 11
Symbol Parameter CML DRIVER DC SPECIFICATIONS V Differential Output Voltage OD Differential Output Voltage V ODp-p (DOUT+) – (DOUT-) ΔV Output Voltage Unbalance OD Offset Voltage – Single-ended & B, Figure 1 Offset Voltage Unbalance ...
Page 12
Symbol Parameter 1.8 V I/O LVCMOS DC SPECIFICATIONS – High Level Input Voltage IH V Low Level Input Voltage IL I Input Current IN V High Level Output Voltage OH V Low Level Output Voltage OL I Output ...
Page 13
Serializer Switching Characteristics Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter t Ser Output Low-to-High LHT Transition Time, Figure 3 t Ser Output High-to-Low HLT Transition Time, Figure 3 t Input Data - Setup Time, DIS ...
Page 14
Symbol Parameter t LVCMOS CHL High-to-Low Transition Time, Figure 10 t Data Valid before CLKOUT – ROS Set Up Time, Figure 14 t Data Valid after CLKOUT – ROH Hold Time, Figure 14 t Deserializer Lock Time, DDLT Figure 13 ...
Page 15
Symbol Parameter t Hold time for a start or a HD;STA repeated start condition, Figure 18 t Set Up time for a start or a SU:STA repeated start condition, Figure 18 t Data Hold Time, HD;DAT Figure 18 t Data ...
Page 16
AC Timing Diagrams and Test Circuits FIGURE 4. Serializer Input CLKIN Waveform and Set and Hold Times www.national.com FIGURE 1. Serializer Test Circuit FIGURE 2. Serializer Output Waveforms FIGURE 3. Serializer Output Transition Times 16 30065346 30065330 30065347 30065331 ...
Page 17
FIGURE 5. Serializer Lock Time FIGURE 6. Serializer Disable Time FIGURE 7. Serializer Latency Delay 17 30065348 30065349 30065310 www.national.com ...
Page 18
FIGURE 8. Serializer Output Jitter FIGURE 9. Checkerboard Data Pattern FIGURE 10. Deserializer LVCMOS Transition Times FIGURE 11. Deserializer Delay – Latency 18 30065350 30065332 30065305 30065311 ...
Page 19
FIGURE 12. Deserializer Disable Time (OSS_SEL = 0) FIGURE 13. Deserializer PLL Lock Times and PDB TRI-STATE™ Delay FIGURE 14. Deserializer Output Data Valid (Setup and Hold) Times with SSCG = Off 19 30065313 30065314 30065335 www.national.com ...
Page 20
FIGURE 15. Deserializer Output Data Valid (Setup and Hold) Times with SSCG = On www.national.com FIGURE 16. Receiver Input Jitter Tolerance FIGURE 17. BIST PASS Waveform 20 30065334 30065316 30065352 ...
Page 21
FIGURE 18. Serial Control Bus Timing Diagram 21 30065336 www.national.com ...
Page 22
Functional Description The DS92LV2411 / DS92LV2412 chipset transmits and re- ceives 24-bits of data and 3 control signals over a single serial CML pair operating at 140 Mbps to 1.4 Gbps. The serial stream also contains an embedded clock, video ...
Page 23
This encoding process helps to prevent static data patterns on the serial stream. The resulting frequency content of the serial stream ranges from the parallel clock frequency to the nyquist rate. For example, ...
Page 24
Channel Link II data encoding which provides ran- domization, scrambling, and DC balanacing of the data. The Des includes multiple features to reduce EMI associated with data ...
Page 25
TABLE 7. SSCG Configuration (LF_MODE = H) — Des Output SSC[3:0] Inputs LH_MODE = MHz) SSC3 SSC2 ...
Page 26
TABLE 8. OSS_SEL and PDB Configuration — Des Outputs INPUTS Serial PDB Input Static H Static H Active H INPUTS Embedded CLK NOTE * Present ≠ * NOTE — Absent and OSC_SEL FIGURE 21. Des Outputs ...
Page 27
FIGURE 22. Des Outputs with Output State Select High (OSS_SEL = H) TABLE 10. OSC_SEL (Oscillator) Configuration OSC_SEL[2:0] INPUTS OSC_SEL2 OSC_SEL1 FIGURE 23. Des ...
Page 28
Des — OP_LOW — Optional The OP_LOW feature is used to hold the LVCMOS outputs, except for the LOCK output LOW state. When the OP_LOW feature is enabled, the LVCMOS outputs will be held at logic LOW while ...
Page 29
Des — Clock Edge Select (RFB) The RFB pin determines the edge that the data is strobed on. If RFB is High, output data is strobed on the Rising edge of the CLKOUT. If RFB is Low, data is strobed ...
Page 30
C1 bits does not reconstruct the expected clock signal, the LOCK pin will switch Low. The combination of the LOCK www.national.com and At-Speed BIST PASS pin provides a powerful tool for system evaluation and performance monitoring. FIGURE 27. BIST ...
Page 31
Optional Serial Bus Control The Ser and Des may also be configured by the use of a serial control bus that is I2C protocol compatible. By default, the I2C reg_0x00'h is set to 00'h and all configuration is set by ...
Page 32
TABLE 13. SERIALIZER — Serial Bus Control Registers ADD ADD Register Name Bit(s) (dec) (hex Ser Config 1 3 Device ID 6 De-Emphasis 7:5 Control 3:0 www.national.com FIGURE 30. Serial Control Bus — READ ...
Page 33
TABLE 14. DESERIALIZER — Serial Bus Control Registers ADD ADD Register Name Bit(s) (dec) (hex Des Config 3 Slave Des Features ...
Page 34
ADD ADD Register Name Bit(s) (dec) (hex Des Features 2 7:5 3 ROUT Config 6:0 www.national.com R/W Defa Function ult (bin) R/W 000 EQ Gain 4 R Enable R/W 0000 SSC 7 R/W 0 ...
Page 35
Applications Information DISPLAY APPLICATION The DS92LV2411/DS92LV2412 chipset is intended for inter- face between a host (graphics processor) and a Display. It supports an 24-bit color depth (RGB888 RGB888 ap- plication, 24 color bits (D[23:0), Pixel Clock (CLKIN) and ...
Page 36
Figure 33 shows a typical connection diagram of the DS92LV2412 Des in pin/strap control mode for a 24-bit ap- plication. The CML inputs utilize 0.1 µF coupling capacitors to the line and the receiver provides internal termination. Bypass capacitors are ...
Page 37
Power Up Requirements and PDB Pin The VDD (V and V ) supply ramp should be faster than DDn DDIO 1.5 ms with a monotonic rise. If slower then 1.5 ms then a capacitor on the PDB pin is needed ...
Page 38
Physical Dimensions 48–pin LLP Package (7 7 0.8 mm, 0.5 mm pitch) 60–pin LLP Package (9 9 0.8 mm, 0.5 mm pitch) www.national.com inches (millimeters) unless otherwise noted NS Package Number SQA48A ...
Page 39
Notes 39 www.national.com ...
Page 40
... For more National Semiconductor product information and proven design tools, visit the following Web sites at: www.national.com Products Amplifiers www.national.com/amplifiers Audio www.national.com/audio Clock and Timing www.national.com/timing Data Converters www.national.com/adc Interface www.national.com/interface LVDS www.national.com/lvds Power Management www.national.com/power Switching Regulators www.national.com/switchers LDOs www.national.com/ldo LED Lighting www ...