PCA9510AD,112 NXP Semiconductors, PCA9510AD,112 Datasheet - Page 6

• Manufacturer Part Number: PCA9510AD,112
• Description: IC I2C/SMBUS BUFF 8-SOIC
• Manufacturer: NXP Semiconductors
• Type: Bufferr

Specifications of PCA9510AD,112

• Tx/rx Type: I²C Logic
• Delay Time: 35ns
• Capacitance - Input: 1.9pF
• Voltage - Supply: 2.7 V ~ 5.5 V
• Current - Supply: 6mA
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (3.9mm Width)
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-3357-5; 935280025112; PCA9510AD

NXP Semiconductors
PCA9510A_4
Product data sheet
8.3 Maximum number of devices in series
Each buffer adds about 0.1 V dynamic level offset at 25 C with the offset larger at higher
temperatures. Maximum offset (V
level at the signal origination end (master) is dependent upon the load and the only
specification point is the I
lightly loaded the V
after four buffers would be 0.5 V, which is only about 0.1 V below the threshold of the
rising edge accelerator (about 0.6 V). With great care a system with four buffers may
work, but as the V
the rising edge accelerator thus introducing false clock edges. Generally it is
recommended to limit the number of buffers in series to two, and to keep the load light to
minimize the offset.
The PCA9510A (rise time accelerator is permanently disabled) and the PCA9512A (rise
time accelerator can be turned off) are a little different with the rise time accelerator turned
off because the rise time accelerator will not pull the node up, but the same logic that turns
on the accelerator turns the pull-down off. If the V
detected, the pull-down will turn off and will not turn back on until a falling edge is
detected.
Consider a system with three buffers connected to a common node and communication
between the Master and Slave B that are connected at either end of buffer A and buffer B
in series as shown in
V
Slave B and then from Slave B to Master. Before the direction change you would observe
V
of buffer B and buffer C would be ~0.5 V, but Slave B is driving 0.4 V, so the voltage at
Slave B is 0.4 V. The output of buffer C is ~0.5 V. When the Master pull-down turns off, the
input of buffer A rises and so does its output, the common node, because it is the only part
driving the node. The common node will rise to 0.5 V before buffer B’s output turns on, if
the pull-up is strong the node may bounce. If the bounce goes above the threshold for the
rising edge accelerator ~0.6 V the accelerators on both buffer A and buffer C will fire
contending with the output of buffer B. The node on the input of buffer A will go HIGH as
will the input node of buffer C. After the common node voltage is stable for a while the
rising edge accelerators will turn off and the common node will return to ~0.5 V because
the buffer B is still on. The voltage at both the Master and Slave C nodes would then fall to
~0.6 V until Slave B turned off. This would not cause a failure on the data line as long as
the return to 0.5 V on the common node (~0.6 V at the Master and Slave C) occurred
before the data set-up time. If this were the SCL line, the parts on buffer A and buffer C
would see a false clock rather than a stretched clock, which would cause a system error.
Fig 4.
OL
IL
at the input of buffer A of 0.3 V and its output, the common node, is ~0.4 V. The output
of Slave B (when acknowledging) is 0.4 V with the direction changing from Master to
System with 3 buffers connected to common node
OL
OL
moves up from 0.1 V, noise or bounces on the line will result in firing
Figure
may be ~0.1 V. Assuming V
Rev. 04 — 18 August 2009
MASTER
2
C-bus specification of 3 mA will produce V
4. Consider if the V
offset
buffer A
) is 0.150 V with a 10 k pull-up resistor. The LOW
common
Hot swappable I
node
OL
buffer C
buffer B
IL
OL
at the input of buffer A is 0.3 V and the
is above ~0.6 V and a rising edge is
= 0.1 V and V
2
SLAVE C
SLAVE B
C-bus and SMBus bus buffer
002aab581
offset
PCA9510A
OL
< 0.4 V, although if
© NXP B.V. 2009. All rights reserved.
= 0.1 V, the level
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