P82B96TD,112 NXP Semiconductors, P82B96TD,112 Datasheet
P82B96TD,112
Specifications of P82B96TD,112
935262295112
P82B96TD
P82B96TD
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P82B96TD,112 Summary of contents
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P82B96 Dual bidirectional bus buffer Rev. 08 — 10 November 2009 1. General description The P82B96 is a bipolar IC that creates a non-latching, bidirectional, logic interface between the normal C-bus logic signals to similar buses having ...
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... NXP Semiconductors 3. Applications I Interface between Interface between I I Simple conversion of I hardware, for example, via compatible PCA82C250 I Interfaces with opto-couplers to provide opto-isolation between I 400 kHz 4. Ordering information Table 1. Type number P82B96DP P82B96PN P82B96TD P82B96TD/S900 4.1 Ordering options Table 2. Type number P82B96DP ...
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... NXP Semiconductors 5. Block diagram Fig 1. 6. Pinning information 6.1 Pinning P82B96PN GND 002aab977 Fig 2. Pin configuration for DIP8 6.2 Pin description Table 3. Symbol GND P82B96_8 Product data sheet P82B96 1 Sx (SDA (SCL) Block diagram of P82B96 P82B96TD P82B96TD/S900 GND 4 002aab978 Fig 3. ...
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... NXP Semiconductors 7. Functional description Refer to The P82B96 has two identical buffers allowing buffering of both of the I SCL) signals. Each buffer is made up of two logic signal paths, a forward path from the 2 I C-bus interface pin which drives the buffered bus, and a reverse signal path from the buffered bus input to drive the I • ...
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... NXP Semiconductors special ‘buffered LOW’ is applied to the Sx/Sy of another P82B96 that second P82B96 will not recognize ‘regular I The Sx/Sy side of P82B96 may not be connected to similar buffers that rely on special logic thresholds for their operation, for example PCA9511, PCA9515, or PCA9518. The ...
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... NXP Semiconductors 9. Characteristics Table 5. Characteristics T = +25 C; voltages are specified with respect to GND with V amb Symbol Parameter Power supply V supply voltage CC I supply current CC I additional quiescent CC supply current Bus pull-up (load) voltages and currents maximum input/output Sx Sy voltage static output loading on ...
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... NXP Semiconductors Table 5. Characteristics …continued T = +25 C; voltages are specified with respect to GND with V amb Symbol Parameter Input logic switching threshold voltages input logic voltage LOW on normal input logic level HIGH Sx Sy threshold dV /dT, temperature coefficient Sx dV /dT of input thresholds ...
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... NXP Semiconductors Table 5. Characteristics …continued T = +25 C; voltages are specified with respect to GND with V amb Symbol Parameter T buffer time delay on fall delay V to falling input between input switching threshold, and output falling buffer time delay on rise delay V to rising input between ...
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... NXP Semiconductors 1000 V OL (mV) 800 600 400 typical and limits over temperature OL (1) Maximum (2) Typical (3) Minimum Fig function of junction temperature 0.2 mA) OL 1000 V IL(max) (mV) 800 600 400 200 changes over temperature range IL(max) Fig function of junction temperature IL(max) V Fig 9. V that guarantees bus release limit over temperature ...
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... NXP Semiconductors 10. Application information Refer to AN460 and AN255 for more application detail. Fig 10. Interfacing an ‘I Fig 11. Galvanic isolation of I SDA SCL Fig 12. Long distance I P82B96_8 Product data sheet + C-bus SDA 1 P82B96 / 2 2 C’ type of bus with different logic levels + C-bus SDA ...
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... NXP Semiconductors Figure 13 in applications that involve plug and socket connections and long cables that may become damaged. A simple circuit is added to monitor the SDA bus, and if its LOW time exceeds the design value, then the master bus is disconnected. P82B96 will free all its I/Os if its supply is removed, so one option is to connect its V say, the 74LVC family ...
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... NXP Semiconductors Figure 14 calculating with lumped wiring capacitance yields reasonable approximations to actual timing, even 25 meters of cable is better treated using transmission line theory. Flat ribbon cables connected as shown, with the bus signals on the outer edge, will have a characteristic impedance in the range 100 ...
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... NXP Semiconductors V CC1 R2 R2 SCL C-BUS MASTER SDA Sy P82B96 C2 C2 GND Fig 14. Driving ribbon or flat telephone cables P82B96_8 Product data sheet +V cable drive cable propagation delay 5 ns/m BAT54A BAT54A Rev. 08 — 10 November 2009 P82B96 Dual bidirectional bus buffer SCL SLAVE( SDA ...
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Table 6. Examples of bus capability Refer to Figure 14 CC1 CC2 cable ( ) ( ) (pF 750 2.2 k 400 ...
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... NXP Semiconductors 10.1 Calculating system delays and bus clock frequency for a Fast mode system local master bus V CCM SCL MASTER 2 I C-BUS GND (0 V) Effective delay of SCL at slave: 255 + 17V volts. Fig 15. Falling edge of SCL at master is delayed by the buffers and bus fall times ...
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... NXP Semiconductors local master bus V CCM SDA MASTER 2 I C-BUS GND (0 V) Effective delay of SDA at master = 270 + 0.2RsCs + 0.7 (RbCb + RmCm) ns Fig 17. Rising edge of SDA at slave is delayed by the buffers and bus rise times Figure 15, with relatively large capacitance, linking two Fast mode I simplifi ...
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... NXP Semiconductors edge from the master reaching the slave the SCL rising edge SDA, reaching the master The master microcontroller should be programmed to produce a nominal SCL LOW period = (1300 + A minimum SCL HIGH period of 600 ns. Then a check should be made to ensure the cycle time is not shorter than the minimum 2500 ns. If found necessary, just increase either clock period ...
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... NXP Semiconductors 400 800 1200 Frequency = 624 kHz Fig 19. Propagation (Sx pull- pull- 10.2 Negative undershoot below absolute minimum value The reason why the IC pin reverse voltage on pins Tx and specified at such a low value, 0 not that applying larger voltages is likely to cause damage but that it is expected that, in normal applications, there is no reason why larger DC voltages will be applied. This ‘ ...
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... NXP Semiconductors Figure 21 “Diode characteristic curve” DC specification was selected. The current near zero at 0.55 V. The P82B96 is allowed to operate with +125 C junction and that would cause this diode voltage to decrease by 100 publish 0.3 V just to have some extra margin. Remark: You should not be concerned about the transients generated on the wiring by a P82B96 in normal applications and that is input to the Tx/Rx or Ty/Ry pins of another P82B96 ...
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... NXP Semiconductors 10.2.1 Example with questions and answers Question falling edge measure undershoot at 800 mV at the linked Tx, Rx pins of the P82B96 that is generating the LOW, but the P82B96 data sheet specifies minimum 0.3 V. Does this mean that we violate the data sheet absolute value? Answer: For P82B96 the 0 ...
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... NXP Semiconductors Question: We have 2 meters of cable in a bus that joins the Tx/Rx sides of two P82B96 devices. When one Tx drives LOW the other P82B96 Tx/Rx is driven to 0.8 V for over 50 ns. What is the expected value and the theoretically allowed value of undershoot? Answer: Because the cable joining the two P82B96s is a ‘transmission line’ that will ...
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... NXP Semiconductors Question add 100 smaller. Is this a good idea? Answer: No not necessary to add any resistance. When the logic signal generated P82B96 drives long traces or wiring with ICs other than P82B96 being driven, then adding a Schottky diode (BAT54A) as shown in wiring undershoot to a value that will not cause conduction of the IC’s internal diodes. ...
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... NXP Semiconductors 11. Package outline DIP8: plastic dual in-line package; 8 leads (300 mil pin 1 index 1 DIMENSIONS (inch dimensions are derived from the original mm dimensions UNIT max. min. max. mm 4.2 0.51 3.2 inches 0.17 0.02 0.13 Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. ...
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... NXP Semiconductors SO8: plastic small outline package; 8 leads; body width 3 pin 1 index 1 DIMENSIONS (inch dimensions are derived from the original mm dimensions) A UNIT max. 0.25 1.45 mm 1.75 0.25 0.10 1.25 0.010 0.057 inches 0.069 0.01 0.004 0.049 Notes 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. ...
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... NXP Semiconductors TSSOP8: plastic thin shrink small outline package; 8 leads; body width pin 1 index 1 e DIMENSIONS (mm are the original dimensions UNIT max. 0.15 0.95 mm 1.1 0.25 0.05 0.80 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm maximum per side are not included. ...
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... NXP Semiconductors 12. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description” . 12.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits ...
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... NXP Semiconductors 12.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see reducing the process window • Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board • ...
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... NXP Semiconductors Fig 28. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description” . 13. Soldering of through-hole mount packages 13.1 Introduction to soldering through-hole mount packages This text gives a very brief insight into wave, dip and manual soldering. ...
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... NXP Semiconductors 13.4 Package related soldering information Table 9. Package CPGA, HCPGA DBS, DIP, HDIP, RDBS, SDIP, SIL [2] PMFP [1] For SDIP packages, the longitudinal axis must be parallel to the transport direction of the printed-circuit board. [2] For PMFP packages hot bar soldering or manual soldering is suitable. ...
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... NXP Semiconductors 15. Revision history Table 11. Revision history Document ID Release date P82B96_8 20091110 • Modifications: Table 4 “Limiting • Added P82B96_7 20090212 P82B96_6 20080131 P82B96_5 20060127 P82B96_4 20040329 (9397 750 12932) P82B96_3 20030402 (9397 750 11351) P82B96_2 20030220 (9397 750 11093) P82B96_1 ...
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... Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...
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... NXP Semiconductors 18. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 4 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 4.1 Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 2 5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 7 Functional description . . . . . . . . . . . . . . . . . . . 4 8 Limiting values Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 6 10 Application information 10.1 Calculating system delays and bus clock frequency for a Fast mode system ...