P82B96TD,112 NXP Semiconductors, P82B96TD,112 Datasheet - Page 8

• Manufacturer Part Number: P82B96TD,112
• Description: IC I2C BUS BUFFER DUAL 8-SOIC
• Manufacturer: NXP Semiconductors
• Type: Bufferr

Specifications of P82B96TD,112

• Package / Case: 8-SOIC (3.9mm Width)
• Tx/rx Type: I²C Logic
• Delay Time: 5.0ns
• Capacitance - Input: 7pF
• Voltage - Supply: 2 V ~ 15 V
• Current - Supply: 900µA
• Mounting Type: Surface Mount
• Logic Family: P82B
• Supply Voltage (max): 15 V
• Supply Voltage (min): 2 V
• Maximum Operating Temperature: 85 C
• Mounting Style: SMD/SMT
• Maximum Power Dissipation: 300 mW
• Minimum Operating Temperature: - 40 C
• Number Of Lines (input / Output): 4 / 2
• Propagation Delay Time: 90 ns
• Logic Type: Bus Buffer
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: OM6285 - EVAL BOARD I2C-2002-1A568-4002 - DEMO BOARD I2C
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-3982-5; 935262295112; P82B96TD; P82B96TD

NXP Semiconductors
Table 5.
T
[1]
[2]
[3]
[4]
[5]
P82B96_8
Product data sheet
Symbol
T
V
V
to V
T
V
V
to V
Input capacitance
C
amb
fall delay
rise delay
Rx
Sx
Rx
Sx
i
, V
, V
Sy
Sy
Limit data for +125 C applies to P82B96TD/S900 version. It is guaranteed by design/characterization, but not by 100 % test.
The minimum value requirement for pull-up current, 200 A, guarantees that the minimum value for V
the minimum V
While the tolerances on absolute levels allow a small probability the LOW from one Sx output is recognized by an Sx input of another
P82B96, this has no consequences for normal applications. In any design the Sx pins of different ICs should never be linked because
the resulting system would be very susceptible to induced noise and would not support all I
The output logic LOW depends on the sink current. For scaling, see Application Note AN255 .
The input logic threshold is independent of the supply voltage.
The fall time of V
The fall time of V
The rise time of V
The rise time of V
to
to
= +25 C; voltages are specified with respect to GND with V
Ry
Ry
Characteristics
Parameter
buffer time delay on
falling input between
V
threshold, and V
output falling 50 %
buffer time delay on
rising input between
V
threshold, and V
output reaching 50 %
V
input capacitance
Rx
Rx
CC
= input switching
= input switching
Sx
Tx
Sx
input HIGH level to eliminate any possibility of latching. The specified difference is guaranteed by design within any IC.
Tx
Sx
from 5 V to 2.5 V in the test is approximately 15 ns.
from 5 V to 2.5 V in the test is approximately 50 ns.
from 0 V to 2.5 V in the test is approximately 20 ns.
from 0.9 V to 2.5 V in the test is approximately 70 ns.
…continued
Sx
Sx
Conditions
R
no capacitive load;
V
R
no capacitive load;
V
effective input
capacitance of any
signal pin measured
by incremental bus
rise times
CC
CC
Sx
Sx
pull-up = 1500 ;
pull-up = 1500 ;
= 5 V
= 5 V
Rev. 08 — 10 November 2009
CC
= 5 V, unless otherwise specified.
Min
-
-
-
T
amb
Typ
250
270
= +25 C
-
2
C-bus operating modes.
Max
7
-
-
Dual bidirectional bus buffer
Sx
output LOW will always exceed
T
amb
Min
-
-
-
+125 C
= 40 C to
© NXP B.V. 2009. All rights reserved.
P82B96
[1]
Max
7
-
-
Unit
ns
ns
pF
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