PCA9547PW,112 NXP Semiconductors, PCA9547PW,112 Datasheet - Page 6

• Manufacturer Part Number: PCA9547PW,112
• Description: IC MUX 8CH I2C BUS 24-TSSOP
• Manufacturer: NXP Semiconductors

Specifications of PCA9547PW,112

• Package / Case: 24-TSSOP
• Applications: Translating Multiplexer
• Interface: I²C, SMBus
• Voltage - Supply: 2.3 V ~ 3.6 V, 4.5 V ~ 5.5 V
• Mounting Type: Surface Mount
• Product: Decoders, Encoders, Multiplexers & Demultiplexers
• Logic Family: PCA
• Number Of Lines (input / Output): 4.0 / 16.0
• Propagation Delay Time: 0.3 ns
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.3 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Number Of Input Lines: 4.0
• Number Of Output Lines: 16.0
• Power Dissipation: 400 mW
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 568-3381-5; 935280789112; PCA9547PW

NXP Semiconductors
6. Functional description
PCA9547_3
Product data sheet
6.2.1 Control register definition
6.1 Device addressing
6.2 Control register
Following a START condition, the bus master must output the address of the slave it is
accessing. The address of the PCA9547 is shown in
internal pull-up resistors are incorporated on the hardware selectable address pins and
they must be pulled HIGH or LOW.
The last bit of the slave address defines the operation to be performed. When set to
logic 1 a read is selected, while a logic 0 selects a write operation.
Following the successful acknowledgement of the slave address, the bus master will send
a byte to the PCA9547, which will be stored in the Control register. If multiple bytes are
received by the PCA9547, it will save the last byte received. This register can be written
and read via the I
A SCx/SDx downstream pair, or channel, is selected by the contents of the control
register. This register is written after the PCA9547 has been addressed. The 4 LSBs of
the control byte are used to determine which channel is to be selected. When a channel is
selected, the channel will become active after a STOP condition has been placed on the
I
made active, so that no false conditions are generated at the time of connection.
2
Fig 5.
Fig 6.
C-bus. This ensures that all SCx/SDx lines will be in a HIGH state when the channel is
Slave address
Control register
2
C-bus.
Rev. 03 — 10 July 2009
X
7
1
X
6
1
fixed
enable bit
X
5
1
X
4
0
B3
3
A2
channel selection bits
8-channel I
selectable
hardware
B2
2
A1
(read/write)
B1
002aaa963
Figure
1
A0 R/W
002aaa962
B0
0
2
C-bus multiplexer with reset
5. To conserve power, no
PCA9547
© NXP B.V. 2009. All rights reserved.
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