LA-ISPPAC-POWR1014-01TN48E Lattice, LA-ISPPAC-POWR1014-01TN48E Datasheet - Page 23

• Manufacturer Part Number: LA-ISPPAC-POWR1014-01TN48E
• Description: IC, PROG POWER SUPPLY SUPERVISOR TQFP-48
• Manufacturer: Lattice
• Series: ispPAC®r

Specifications of LA-ISPPAC-POWR1014-01TN48E

• Input Voltage: 4.5V
• Supply Voltage Range: 2.8V To 3.96
• No. Of Pins: 48
• Operating Temperature Range: -40°C To +105°C
• No. Of Macrocells: 24
• Termination Type: SMD
• Supply Voltage Min: 2.8V
• Rohs Compliant: Yes
• Applications: General Purpose
• Voltage - Input: -0.3 V ~ 5.9 V
• Voltage - Supply: 2.8 V ~ 3.96 V
• Current - Supply: 20mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: *
• Package / Case: *
• Filter Terminals: SMD
• Frequency: 25MHz
• Input Voltage Primary Max: 4.5V
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Lattice Semiconductor
SCL provides a synchronous clock signal. The SMBAlert line is only present in SMBus systems. The 7-bit I
address of the POWR1014A is fully programmable through the JTAG port.
Figure 14. LA-ispPAC-POWR1014A in I
In both the I
ter device generates the SCL clock signal and coordinates all data transfers to and from a number of slave devices.
The LA-ispPAC-POWR1014A is configured as a slave device, and cannot independently coordinate data transfers.
Each slave device on a given I
7-bit addressing portion of the standard. Any 7-bit address can be assigned to the LA-ispPAC-POWR1014A device
by programming through JTAG. When selecting a device address, one should note that several addresses are
reserved by the I
assure bus compatibility. Table 6 lists these reserved addresses.
Table 6. I
The LA-ispPAC-POWR1014A’s I
data write transaction (Figure 15) consists of the following operations:
1. Start the bus transaction
2. Transmit the device address (7 bits) along with a low write bit
3. Transmit the address of the register to be written to (8 bits)
2
C/SMBus Reserved Slave Device Addresses
SDA
V+
2
C and SMBus protocols, the bus is controlled by a single MASTER device at any given time. This mas-
0000 000
0000 000
0000 001
0000 010
0000 011
0000 1xx
0001 000
0001 100
0101 000
0110 111
1100 001
1111 0xx
1111 1xx
Address
MICROPROCESSOR
(I
2
2
SCL
C and/or SMBus standards, and should not be assigned to LA-ispPAC-POWR1014A devices to
C MASTER)
INTERRUPT
R/W bit
2
C bus is assigned a unique address. The LA-ispPAC-POWR1014A implements the
0
1
x
x
x
x
x
x
x
x
x
x
x
2
C/SMBus interface allows data to be both written to and read from the device. A
SDA/SMDAT (DATA)
SCL/SMCLK (CLOCK)
SMBALERT
General Call Address
Start Byte
CBUS Address
Reserved
Reserved
HS-mode master code
NA
NA
NA
NA
NA
10-bit addressing
Reserved
I
2
2
LA-ispPAC-POWR1014/A Automotive Family Data Sheet
C/SMBUS System
C function Description
SDA
POWR1014A
(I
2
C SLAVE)
23
SCL
OUT5/
SMBA
General Call Address
Start Byte
CBUS Address
Reserved
Reserved
HS-mode master code
SMBus Host
SMBus Alert Response Address
Reserved for ACCESS.bus
Reserved for ACCESS.bus
SMBus Device Default Address
10-bit addressing
Reserved
SMBus Function
SDA
POWR1014A
(I
2
C SLAVE)
SCL
OUT5/
SMBA
To Other
Devices
I
2
C
2
C