STDVE103ABTR STMicroelectronics, STDVE103ABTR Datasheet - Page 16

• Manufacturer Part Number: STDVE103ABTR
• Description: IC EQUALIZER TMDS/HDMI 64-TQFP
• Manufacturer: STMicroelectronics

Specifications of STDVE103ABTR

• Applications: TV
• Interface: I²C
• Voltage - Supply: 3.3V, 5V
• Package / Case: 64-TQFP, 64-VQFP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-8384-2

Functional description
4.5
4.6
16/44
I
The device contains two identical bidirectional open-drain, non-inverting buffer circuits that
enable I
STDVE103A buffers both the serial data (DDC SDA) and serial clock (DDC SCL) on the I
bus, while retaining all the operating modes and features of the I
two buses of 400 pF bus capacitance to be connected in an I
are operational from a supply voltage of 3.0 to 3.6 V.
The I
STDVE103A enables the system designer to isolate the two halves of a bus,
accommodating more I
buses, one at 5 V and the other at 3.3 V or a 400 kHz and 100 kHz bus, where the 100 kHz
bus is isolated when 400 kHz operation of the other bus is required. The STDVE103A can
be used to run the I
Two or more STDVE103As cannot be connected in series. The STDVE103A design does
not allow this configuration. Since there is no direction pin, slightly different “legal” low
voltage levels are used to avoid lock-up conditions between the input and output. A valid low
applied at the input of STDVE103A is propagated as a buffered low with a slightly higher
value on the enabled outputs.
When this buffered low is applied to another STDVE103A in series, the second STDVE103A
will not recognize it as a valid low and will not propagate it as a buffered low again.
The S1 and S2 (SEL) lines act as control signals for the corresponding A, B or C ports. Note
that the SEL line has an internal pull-down resistor. The SEL line should not change state
during an I
enabling part way through a bus cycle could confuse the I
input should change state only when the global bus and the repeater port are in idle state, to
prevent system failures.
The output low levels for each internal buffer are approximately 0.5 V, but the input voltage
of each internal buffer must be 70 mV or more below the output low level, when the output
internally is driven low. This prevents a lock-up condition from occurring when the input low
condition is released.
As with the standard I
levels on the buffered bus. The STDVE103A has standard open collector configuration of
the I
repeater must have a pull up resistor.
This part is designed to work with standard mode and fast mode I
mode I
in a generic I
Under certain conditions, higher termination currents can be used.
Power-down condition
The HL combination of S1, S2 is used to disable most of the internal circuitry of
STDVE103A that puts the device in a low power mode of operation.
2
C DDC line repeater
2
2
C bus. The size of the pull up resistors depends on the system, but each side of the
C bus capacitance limit of 400 pF restricts the number of devices and bus length. The
2
2
C devices only specify 3 mA output drive, this limits the termination current to 3 mA
C DDC bus lines to be extended without degradation in system performance. The
2
C operation, because disabling during bus operation hangs the bus and
2
C system where standard mode devices and multiple masters are possible.
2
C bus at both 5 V and 3.3 V interface levels.
2
C system, pull up resistors are required to provide the logic high
2
C devices or longer trace lengths. It can also be used to run two
Doc ID 14911 Rev 4
2
C parts being enabled. The SEL
2
C application. These buffers
2
C system. This enables
2
C devices. Standard
STDVE103A
2
C