PI7C9X7954AFDE Pericom Semiconductor, PI7C9X7954AFDE Datasheet - Page 29

• Manufacturer Part Number: PI7C9X7954AFDE
• Description: IC PCIE-TO-UART BRIDGE 128LQFP
• Manufacturer: Pericom Semiconductor

Specifications of PI7C9X7954AFDE

• Applications: PCIe-to-Uart Bridge
• Interface: Advanced Configuration Power Interface (ACPI)
• Voltage - Supply: 1.8V, 3.3V
• Package / Case: 128-LQFP
• Mounting Type: Surface Mount
• Transmitter And Receiver Fifo Counter: Yes
• Package Type: LQFP
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

6.2.14. CAPABILITIES POINTER REGISTER – OFFSET 34h
6.2.15. INTERRUPT LINE REGISTER – OFFSET 3Ch
6.2.16. INTERRUPT PIN REGISTER – OFFSET 3Ch
6.2.17. POWER MANAGEMENT CAPABILITY ID REGISTER – OFFSET 80h
6.2.18. NEXT ITEM POINTER REGISTER – OFFSET 80h
6.2.19. POWER MANAGEMENT CAPABILITIES REGISTER – OFFSET 80h
September 2009 – Revision 1.3
Pericom Semiconductor
BIT
7:0
BIT
7:0
BIT
15:8
BIT
7:0
BIT
15:8
BIT
18:16
19
20
21
24:22
25
26
FUNCTION
Interrupt Line
FUNCTION
Enhanced
Capabilities ID
Next Item Pointer
FUNCTION
Capabilities Pointer
FUNCTION
Interrupt Pin
FUNCTION
FUNCTION
Power Management
Revision
PME# Clock
Auxiliary Power
Device Specific
Initialization
AUX Current
D1 Power State
Support
D2 Power State
Support
09-0088
TYPE
TYPE
TYPE
TYPE
TYPE
TYPE
RW
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
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DESCRIPTION
Used to communicate interrupt line routing information. POST
software will write the routing information into this register as it
initializes and configures the system.
Reset to 00h.
DESCRIPTION
Read as 01h to indicate that these are power management enhanced
capability registers.
DESCRIPTION
This optional register points to a linked list of new capabilities
implemented by the device. This default value may be changed by
auto-loading from EEPROM.
The default value is 80h.
DESCRIPTION
Identifies the legacy interrupt Message(s) the device uses.
Reset to 01h.
DESCRIPTION
The pointer points to the Power Management capability register
(8Ch).
Reset to 8Ch.
DESCRIPTION
Read as 011b to indicate the I/O bridge is compliant to Revision 1.1
of PCI Power Management Interface Specifications.
Does not apply to PCI Express. Must be hardwired to 0b.
Read as 1b to indicate the I/O bridge forwards the PME# message in
D3cold and an auxiliary power source is required.
Read as 0b to indicate the I/O bridge does not have device specific
initialization requirements. The default value may be changed by
auto-loading from EEPROM.
Reset as 111b to indicate the I/O bridge need 375 mA in D3 state.
The default value may be changed by auto-loading from EEPROM.
Read as 1b to indicate the I/O bridge supports the D1 power
management state. The default value may be changed by
auto-loading from EEPROM.
Read as 1b to indicate the I/O bridge supports the D2 power
management state. The default value may be changed by
auto-loading from EEPROM.
PCI Express® Quad UART
PI7C9X7954
Datasheet