ADM1024ARUZ ON Semiconductor, ADM1024ARUZ Datasheet - Page 19

• Manufacturer Part Number: ADM1024ARUZ
• Description: IC MONITOR SYS TEMP/VOLT 24TSSOP
• Manufacturer: ON Semiconductor

Specifications of ADM1024ARUZ

• Applications: PC's, PDA's
• Interface: Serial
• Voltage - Supply: 2.8 V ~ 5.5 V
• Package / Case: 24-TSSOP
• Mounting Type: Surface Mount
• Temperature Sensor Function: Temp Sensor
• Output Type: Digital
• Package Type: TSSOP
• Operating Temperature (min): 0C
• Operating Temperature (max): 100C
• Operating Temperature Classification: Commercial
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 5.5V
• Full Temp Accuracy: +/- 2 C , +/- 3 C
• Digital Output - Bus Interface: SMBus
• Digital Output - Number Of Bits: 10 bit
• Supply Voltage (max): 12 V
• Supply Voltage (min): 2.5 V
• Maximum Operating Temperature: + 100 C
• Minimum Operating Temperature: 0 C
• Supply Current: 1.4 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

of alarm input. Figure 31 shows a temperature alarm circuit
using an AD22105 temperature switch sensor. This produces
a low going output when the preset temperature is exceeded,
so the output is inverted by Q1 to make it compatible with the
CI input. Q1 can be almost any small−signal NPN transistor,
or a TTL or CMOS inverter gate may be used if one is
available. See the AD22105 data sheet for information on
selecting R
protective clamp diode to V
chassis intrusion latch and reset it when the ADM1024 is
powered down.
The ADM1024 Interrupt Structure
Figure 32. As each measurement value is obtained and
stored in the appropriate value register, the value and the
limits from the corresponding limit registers are fed to the
high and low limit comparators. The result of each
comparison (1 = out of limit, 0 = in limit) is routed to the
corresponding bit input of the Interrupt Status Registers via
a data demultiplexer and used to set that bit high or low as
appropriate.
each of the Interrupt Status Register Bits. Setting an
Interrupt Mask Bit high forces the corresponding Status Bit
output low, while setting an Interrupt Mask Bit low allows
the corresponding Status Bit to be asserted. After masking,
the status bits are all OR’d together to produce the INT
output, which will pull low if any unmasked status bit goes
high, i.e., when any measured value goes out of limit. The
Figure 31. Using the CI Input with a Temperature Sensor
The chassis intrusion input can also be used for other types
Note: The chassis intrusion input does not have a
The Interrupt Structure of the ADM1024 is shown in
The Interrupt Mask Registers have bits corresponding to
R
SET
SET
.
6
3
TEMPERATURE
AD22105
SENSOR
CC
7
1
2
, as this could pull down the
Q1
R1
10kΩ
V
CC
CI
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19
ADM1024 also has a dedicated output for temperature
interrupts only, the THERM input/output Pin 2. The
function of this is described later.
Register 1 (INT_Enable) is high, and Bit 3 (INT_Clear) is low.
The INT pin has an internal, 100 kW pullup resistor.
VID/IRQ Inputs
reconfigured as interrupt inputs by setting Bit 7 of the
Channel Mode Register (address 16h). In this mode they
operate as level−triggered interrupt inputs, with VID0/IRQ0
to VID2/IRQ2 being active low and VID3/IRQ3 and
VID4/IRQ4 being active high. The individual interrupt
inputs can be enabled or masked by setting or clearing Bits 4
to 6 of the Channel Mode Register and Bits 6 and 7 of
Configuration Register 2 (address 4Ah). These interrupt
inputs are not latched in the ADM1024, so they do not
require clearing as do bits in the Status Registers. However,
the external interrupt source should be cleared once the
interrupt has been services, or the interrupt request will be
reasserted.
Interrupt Clearing
contents of the Register, then clear it. It will remain cleared
until the monitoring cycle updates it, so the next read
operation should not be performed on the register until this
has happened, or the result will be invalid. The time taken for
a complete monitoring cycle is mainly dependent on the
time taken to measure the fan speeds, as described earlier.
is Bit 3 of the Configuration Register, without affecting the
contents of the Interrupt (INT) Status Registers.
Interrupt Status Mirror Registers
updated, the same bit is written to duplicate registers at
addresses 4Ch and 42h. These registers allow a second
management system to access the status data without
worrying about clearing the data. The data in these registers
is for reading only and has no effect on the interrupt output.
The INT output is enabled when Bit 1 of Configuration
The processor voltage ID inputs VID0 to VID4 can be
Reading an Interrupt Status Register will output the
The INT output is cleared with the INT_Clear bit, which
Whenever a bit in one of the Interrupt Status Registers is